Back-end electrically programmable fuse

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME

Interconnection structure, semiconductor device, and method of manufacturing the same

Inverted-T shaped via for reducing adverse stress-migration effects

Method of semiconductor integrated circuit fabrication

Mitigating electromigration, in-rush current effects, IR-voltage drop, and jitter through metal line and via matrix insertion

Semiconductor device with self-aligned contact

Method of preventing pattern collapse

Method for fabricating an interposer

Semiconductor device

Semiconductor device and manufacturing method thereof

Structure of backside copper metallization for semiconductor devices and a fabrication method thereof

Interconnect having air gaps and polymer wrapped conductive lines

Semiconductor package and method of manufacturing the same

Stacked integrated circuits with redistribution lines

Metal line structure and method

Methods of fabricating semiconductor devices with blocking layer patterns

THREE-DIMENSIONAL THREE-PORT BIT CELL AND METHOD OF ASSEMBLING SAME

DISPLAY PANEL, ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME

Array substrate and method of fabricating the same, and liquid crystal display device

Thin film transistor and manufacturing method thereof, array substrate and display device

Memory cell

Wafer-to-wafer bonding structure

Methods for forming fan-out package structure

Pad design for reliability enhancement in packages

Semiconductor device packages, packaging methods, and packaged semiconductor devices

Semiconductor devices including insulating extension patterns between adjacent landing pads and methods of fabricating the same

Electronic device

SEMICONDUCTOR MEMORY DEVICE

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor structure and manufacturing method for the same

Semiconductor device packages, packaging methods, and packaged semiconductor devices

Integrated circuits with an insultating layer and methods for producing such integrated circuits

Array substrate, liquid crystal display panel and display device

MIM capacitors for leakage current improvement

Semiconductor magnetic memory device and method for manufacturing the same

Hybrid copper structure for advance interconnect usage

Interconnect structure and method of forming the same

Semiconductor device

Method and apparatus for back end of line semiconductor device processing

Power rail for preventing DC electromigration

Semiconductor device

Individualised voltage supply of integrated circuits components as protective means against side channel attacks

Embedded semiconductor device package and method of manufacturing thereof

Semiconductor devices and methods of manufacture thereof

Capacitor in post-passivation structures and methods of forming the same

Staggered via redistribution layer (RDL) for a package and a method for forming the same

GOA circuit of array substrate and display apparatus

Interposer test structures and methods

Method for Forming a Vertical Electrical Conductive Connection

Display panel and manufacturing method thereof

SEMICONDUCTOR CONTACT WITH DIFFUSION-CONTROLLED IN SITU INSULATOR FORMATION

ELECTROLESS FILLED CONDUCTIVE STRUCTURES

Self-aligned contact structure

Devices, packaging devices, and methods of packaging semiconductor devices

BACK-END-OF-LINE STACK FOR A STACKED DEVICE

Integrated circuit having main route and detour route for signal transmission and integrated circuit package including the same

Nanoscale interconnects fabricated by electrical field directed assembly of nanoelements

INDUCTOR FORMED ON A SEMICONDUCTOR SUBSTRATE

Electrostatic discharge protection device

Method of manufacturing a semiconductor device

RECONFIGURED WIDE I/O MEMORY MODULES AND PACKAGE ARCHITECTURES USING SAME

PACKAGE STRUCTURE

Semiconductor device and method for manufacturing same

Integrated circuit with guard ring

Interconnect structure with footing region

CIRCUITS INCORPORATING INTEGRATED PASSIVE DEVICES HAVING INDUCTANCES IN 3D CONFIGURATIONS AND STACKED WITH CORRESPONDING DIES

Integrated circuit with guard ring

Semiconductor structures having low resistance paths throughout a wafer

Metal interconnect structure and fabrication method thereof

Array of conductive vias, methods of forming a memory array, and methods of forming conductive vias

Selective formation of conductor nanowires

Device having multiple-layer pins in memory MUX1 layout

Direct die solder of gallium arsenide integrated circuit dies and methods of manufacturing gallium arsenide wafers

Double-sided segmented line architecture in 3D integration

MOL resistor with metal grid heat shield

Self-aligned interconnect with protection layer

Semiconductor structures having low resistance paths throughout a wafer

Semiconductor structures having low resistance paths throughout a wafer

Enhancement of iso-via reliability

Non-hierarchical metal layers for integrated circuits

ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE

Thin film transistor substrate

Methods and structures for multiport memory devices

ROM chip manufacturing structures

Semiconductor device and manufacturing method of the same

Semiconductor device

Semiconductor device

Semiconductor structure and method for manufacturing the same

Semiconductor devices comprising interconnect structures and methods of fabrication

Integrated circuit assembly with cushion polymer layer

Logic cell, semiconductor device including logic cell, and method of manufacturing the logic cell and semiconductor device

Semiconductor device and structure

Multi-level stack having multi-level contact and method

Clock skew adjusting structure

Semiconductor device including a reservoir capacitor

Process for forming package-on-package structures

3D semiconductor device having two layers of transistors

Wire bond support structure and microelectronic package including wire bonds therefrom

Plurality of semiconductor devices in resin with a via

Semiconductor device having trench adjacent to receiving area and method of forming the same

3DIC interconnect devices and methods of forming same

Interconnect structures and fabrication method thereof

Semiconductor device including insulating film having opening portion and conductive film in the opening portion

Semiconductor device including plural types of resistors and manufacturing method of the semiconductor device

REDUCED CAPACITANCE INTERLAYER STRUCTURES AND FABRICATION METHODS

ELECTRONIC DEVICE PACKAGE

3DIC interconnect devices and methods of forming same

Alignment mark design for packages

Vias and methods of formation thereof

Protective via cap for improved interconnect performance

Structure for isolating high speed digital signals in a high density grid array

Semiconductor device and method of manufacturing the same

Physical unclonable interconnect function array

Apparatus and method for placing stressors on interconnects within an integrated circuit device to manage electromigration failures

Manganese oxide hard mask for etching dielectric materials

Directed self assembly of block copolymers to form vias aligned with interconnects

Thin film interconnects with large grains

METHOD OF MANUFACTURING A MICRO-FABRICATED WAFER LEVEL INTEGRATED INDUCTOR OR TRANSFORMER FOR HIGH FREQUENCY SWITCH MODE POWER SUPPLIES

Low parasitic capacitance semiconductor device package

CONDUCTOR DESIGN FOR INTEGRATED MAGNETIC DEVICES

Microelectronic packages having cavities for receiving microelectronic elements

Compact semiconductor package and related methods

RF SWITCH STRUCTURE HAVING REDUCED OFF-STATE CAPACITANCE

Method of planarizing recesses filled with copper

Three dimensional (3D) integrated circuits (ICs) (3DICs) and related systems

Semiconductor device having solderable and bondable electrical contact pads

Metal pad offset for multi-layer metal layout

Semiconductor device having Ti- and N-containing layer, and manufacturing method of same

PLACEMENT OF MONOLITHIC INTER-TIER VIAS (MIVs) WITHIN MONOLITHIC THREE DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs) USING CLUSTERING TO INCREASE USABLE WHITESPAC

Substrate and method of forming the same

Voids in interconnect structures and methods for forming the same

Conductive line patterning

Methods and structures for back end of line integration

Method of fabricating a semiconductor device with reduced leak paths

Wide pin for improved circuit routing

Device embedded substrate and manufacturing method of device embedded substrate

Metal-insulator-metal back end of line capacitor structures

3D stacked IC device with stepped substack interlayer connectors

Composite device with integrated diode

Embedded package and method thereof

Chip package and method for forming the same

Semiconductor device

Chip with programmable shelf life

Interconnect structure and manufacturing method thereof

CORELESS PACKAGING SUBSTRATE, POP STRUCTURE, AND METHODS FOR FABRICATING THE SAME

Via material selection and processing

HIGH DENSITY SRAM ARRAY DESIGN WITH SKIPPED, INTER-LAYER CONDUCTIVE CONTACTS

Slot-shielded coplanar strip-line compatible with CMOS processes

Substrate block for PoP package

Low-stress vias

Semiconductor device and method of manufacturing the same

Integrated circuits with metal-titanium oxide contacts and fabrication methods

Insulator, capacitor with the same and fabrication method thereof, and method for fabricating semiconductor device

Integrated thinfilm resistor and MIM capacitor with a low serial resistance

Integrative resistive memory in backend metal layers

Array substrate and a method for manufacturing the same

MULTI-CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME

Semiconductor device having low dielectric insulating film and manufacturing method of the same

Composite contact plug structure and method of making same

Semiconductor package

Wafer having pad structure

Back-end-of-line (BEOL) interconnect structure

Method for forming semiconductor structure

Staggered power structure in a power distribution network (PDN)

Array substrate, its manufacturing method, and display device

Semiconductor device and layout design system

Semiconductor device and method of producing semiconductor device

Electromagnetic bandgap structure for three dimensional ICS

High density dielectric etch-stop layer

Systems and methods to enhance passivation integrity

Semiconductor device, method of manufacturing thereof, circuit board and electronic apparatus

Wiring substrate

Metal contact structure and method of forming the same in a semiconductor device

Method of forming chip with through silicon via electrode

Semiconductor structure and method of making the same

SINGULATED UNIT SUBSTRATE FOR A SEMICONDCUTOR DEVICE

Package structure with direct bond copper substrate

Zero stand-off bonding system and method

Semiconductor device with integrated hot plate and recessed substrate and method of production

Device including multiple semiconductor chips and multiple carriers

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME

Semiconductor constructions and methods of forming electrically conductive contacts

Three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) tiers, and related 3D integrated circuits (3DICs), 3DIC processor cores, and methods

Ultrasonic transducers in complementary metal oxide semiconductor (CMOS) wafers and related apparatus and methods

Conductive via structure and fabrication method thereof

Interconnect structure and method of forming the same

MIM capacitor structure

Semiconductor interconnect structures

Pattern between pattern for low profile substrate

Circuits incorporating integrated passive devices having inductances in 3D configurations and stacked with corresponding dies

Silicon process compatible trench magnetic device

Organic electroluminescence device and manufacturing method thereof

Interconnect structure for connecting dies and methods of forming the same

Array substrate, display panel and display apparatus

Semiconductor device with output circuit and pad arrangements

Semiconductor devices having conductive pads and methods of fabricating the same

Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP

Semiconductor device

Semiconductor device and semiconductor package

Semiconductor device and method of fabricating the same

Semiconductor devices having through electrodes capped with self-aligned protection layers

Stress mitigation structure for wafer warpage reduction

Method for forming interconnects

Semiconductor devices and methods of fabricating the same

Hydrogen-free silicon-based deposited dielectric films for nano device fabrication

SEMICONDUCTOR DEVICE

Hybrid bonding with uniform pattern density

Method for manufacturing array substrate, array substrate, and display device

Bonding structure for stacked semiconductor devices

Semiconductor device

Electrical interconnection structure and fabrication method thereof

Interconnect structure having large self-aligned vias

Interconnect structure having large self-aligned vias

Integrated circuit assembly with cushion polymer layer

Semiconductor manufacturing method and semiconductor device

Embedded circuit patterning feature selective electroless copper plating

Single exposure in multi-damascene process

Semiconductor structure with anti-etch structure in via and method for manufacturing the same

Etchstop layers and capacitors

Active matrix using hybrid integrated circuit and bipolar transistor

Array Substrate, Method for Preparing the Same and Display Device

Display device having driver IC directly connected to substrate

Crack-stopping structure and method for forming the same

Semiconductor chip including integrated circuit including four transistors of first transistor type and four transistors of second transistor type with electrical connections between various transistors and methods for manufacturing the same

Self-aligned contacts

Via pre-fill on back-end-of-the-line interconnect layer

Method for layout design and structure with inter-layer vias

Scalable interconnect structures with selective via posts

Methods of forming reduced resistance local interconnect structures and the resulting devices

Contact window structure, pixel structure and method for manufacturing thereof

Semiconductor structure and method making the same

Metallization of fluorocarbon-based dielectric for interconnects

CHIP ON FILM PACKAGES INCLUDING PLURALITY OF OUTPUT PADS CONNECTED TO FILM WIRES

Fault containment routing

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

Series resistor over drain region in high voltage device

Semiconductor device

3D packages and methods for forming the same

Semiconductor device having a graphene interconnect

Semiconductor Device and Method Of Manufacturing the Same

Barrier structure for copper interconnect

Patterning approach to reduce via to via minimum spacing

Semiconductor arrangement and formation thereof

Semiconductor device

Method and structure for determining thermal cycle reliability

EVALUATION ELEMENT AND WAFER

Interconnect structure and method of forming same

Barrier structure for copper interconnect

Forming array contacts in semiconductor memories

Integrated circuit package

Method of semiconductor integrated circuit fabrication

Semiconductor device including stacked semiconductor chips

Method for forming carbon nanotubes and carbon nanotube film forming apparatus

COMPONENT, FOR EXAMPLE NMOS TRANSISTOR, WITH ACTIVE REGION WITH RELAXED COMPRESSION STRESSES, AND FABRICATION METHOD

Silicon process compatible trench magnetic device

NAND-connected string of transistors having the electrical channel in a direction perpendicular to a surface of the substrate

Mold chase for integrated circuit package assembly and associated techniques and configurations

PACKAGE STRUCTURE

Thermal vias disposed in a substrate proximate to a well thereof

Embedded die flip-chip package assembly

Semiconductor device comprising metal plug having substantially convex bottom surface

Semiconductor devices and methods of manufacture thereof

Integrated circuit interconnects and methods of making same

ENHANCEMENT OF ISO-VIA RELIABILITY

Three-dimensional (3D) semiconductor devices and methods of fabricating 3D semiconductor devices

Semiconductor device and method of fabricating the same

Semiconductor device and method of manufacturing same

Electronic component having encapsulated wiring board and method for manufacturing the same

Self-aligned via patterning with multi-colored photobuckets for back end of line (BEOL) interconnects

Structure and method for a transformer with magnetic features

Array substrate and method for manufacturing the same, display apparatus

Seal ring structure with a metal pad

Three dimensional circuit including shielded inductor and method of forming same

Through-substrate via formation with improved topography control

Stress migration mitigation utilizing induced stress effects in metal trace of integrated circuit device

Semiconductor chip including region having integrated circuit transistor gate electrodes formed by various conductive structures of specified shape and position and method for manufacturing the same

Selective conductive barrier layer formation

Semiconductor device with resistance circuit

Power Transistor Die with Capacitively Coupled Bond Pad

Manufacturing method of device embedded substrate and device embedded substrate manufactured by this method

Conductive line routing for multi-patterning technology

Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches

Semiconductor device

Method for creating contacts in semiconductor substrates

Phase changing on-chip thermal heat sink

Electropositive metal containing layers for semiconductor applications

Bottom package with metal post interconnections

Photoresist collapse method for forming a physical unclonable function

Semiconductor device having interconnect layer that includes dielectric segments interleaved with metal components

Semiconductor device and method for producing same

Wiring structure and method of manufacturing the same

Method for producing salicide and a carbon nanotube metal contact

Line structure and a method for producing the same

Semiconductor device for reducing coupling capacitance

Functional block stacked 3DIC and method of making same

Grounding dummy gate in scaled layout design

REDUNDANT VIA STRUCTURE FOR METAL FUSE APPLICATIONS

Semiconductor device

Semiconductor device and method for manufacturing the same