Interconnect structure and method

Through via structure extending to metallization layer

Interconnect structure and method of forming the same

DC-to-DC converter and method for fabricating the same

Accessing or interconnecting integrated circuits

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

SEMICONDCUTOR CHIP AND SEMIONDUCOT MODULE

Semiconductor device and method of mounting semiconductor die to heat spreader on temporary carrier and forming polymer layer and conductive layer over the die

Reliable microstrip routing for electronics components

Semiconductor device and a method of manufacturing the same

Semiconductor structure having a plurality of conductive paths

Semiconductor device

Methods of making a monolithic microwave integrated circuit

Display panel, display device, and method for manufacturing display panel

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING SAME

Semiconductor device

SRAM cell connection structure

Semiconductor device with improved contact structure and method of forming same

Semiconductor arrangement with electrostatic discharge (ESD) protection

Impedance controlled electrical interconnection employing meta-materials

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Overlay-tolerant via mask and reactive ion etch (RIE) technique

Semiconductor test structure for MOSFET noise testing

Non-lithographic formation of three-dimensional conductive elements

Semiconductor arrangement and formation thereof

Flexibly-wrapped integrated circuit die

Package substrate structure for enhanced signal transmission and method

Bonding pad structure with dense via array

Semiconductor structures comprising at least one through-substrate via filled with conductive materials

Packages for three-dimensional die stacks

Semiconductor device and IO-cell

Semiconductor device including landing pad

E-fuse structure with methods of fusing the same and monitoring material leakage

Interconnect structure and method of fabricating same

Interconnect structures comprising flexible buffer layers

Organic light-emitting diode display with bottom shields

Three-dimensional semiconductor device

Semiconductor device and method of manufacturing the same

Integrated helical multi-layer inductor structures

Method of forming an interconnect structure with high process margins

Semiconductor device having barrier metal layer

Chip package and method of manufacturing the same

Semiconductor device and method for making same

FABRICATING A VIA

Moisture barrier capacitors in semiconductor components

Semiconductor devices and methods of manufacture thereof

Chip package

Semiconductor structure having an air-gap region and a method of manufacturing the same

Duplicate layering and routing

Method of manufacturing semiconductor device and semiconductor device

Technique for reducing plasma-induced etch damage during the formation of vias in interlayer dielectrics by modified RF power ramp-up

Semiconductor structure with inlaid capping layer and method of manufacturing the same

Memory cell

Thin-film semiconductor device, organic EL display device, and manufacturing methods thereof

SEMICONDUCTOR DEVICE

Shielded device packages having antennas and related fabrication methods

Conductive film and semiconductor device

Method to fabricate copper wiring structures and structures formed thereby

Air gap forming techniques based on anodic alumina for interconnect structures

Semiconductor chip with a dual damascene wire and through-substrate via (TSV) structure

Apparatus, system, and method for wireless connection in integrated circuit packages

Semiconductor device and method of forming thereof

Interconnect structure for semiconductor devices

Staggered via redistribution layer (RDL) for a package and a method for forming the same

Semiconductor structure including stacked structure and method for forming the same

ELECTRONIC COMPONENT MODULE

Semiconductor device and method for fabricating the same

Through via contacts with insulated substrate

Double-sided segmented line architecture in 3D integration

Integrated circuits with improved gap fill dielectric and methods for fabricating same

Semiconductor device and manufacturing method thereof

Metal thin film resistor and process

Multilevel via placement with improved yield in dual damascene interconnection

Integrated semiconductor device

Process for forming package-on-package structures

Three dimensional integrated circuit (3DIC) having a thermally enhanced heat spreader embedded in a substrate

Three-dimensional package structure and the method to fabricate thereof

Method of processing a semiconductor wafer

Cobalt based interconnects and methods of fabrication thereof

METAL INTERCONNECT STRUCTURES AND FABRICATION METHOD THEREOF

Semiconductor device and method of forming fine pitch RDL over semiconductor die in fan-out package

Method of controlling contact hole profile for metal fill-in

Method and apparatus of a three dimensional integrated circuit

Using materials with different etch rates to fill trenches in semiconductor devices

Semiconductor devices with inner via

Thickened stress relief and power distribution layer

Forming functionalized carrier structures with coreless packages

Semiconductor devices having through-substrate via plugs and semiconductor packages including the same

Semiconductor substrate and fabrication method thereof

Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches

Cluster system for eliminating barrier overhang

Diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects

Air-gap forming techniques for interconnect structures

Testing of semiconductor devices and devices, and designs thereof

Self aligned active trench contact

Radio frequency and microwave devices and methods of use

Multichip integration with through silicon via (TSV) die embedded in package

Integrated circuits having crack-stop structures and methods for fabricating the same

Method of creating a maskless air gap in back end interconnections with double self-aligned vias

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects

Self-aligned via patterning with multi-colored photobuckets for back end of line (BEOL) interconnects

INTEGRATED CIRCUITS WITH DUMMY CONTACTS AND METHODS FOR PRODUCING SUCH INTEGRATED CIRCUITS

Semiconductor structure and method making the same

3DIC package and methods of forming the same

Method and layout of an integrated circuit

Finger metal oxide metal capacitor formed in a plurality of metal layers

Integrated circuit packaging system with embedded component and method of manufacture thereof

Method of forming semiconductor device using remote plasma treatment

Semiconductor devices, methods of manufacture thereof, and capacitors

Methods of manufacturing a semiconductor device with non-overlapping slits in-between memory blocks

SEMICONDUCTOR DEVICE

Protective layer for contact pads in fan-out interconnect structure and method of forming same

Semiconductor structure and method for forming the same

Bi-layer hard mask for robust metallization profile

INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME

Surface pre-treatment for hard mask fabrication

Trench interconnect having reduced fringe capacitance

ADVANCED INTERCONNECT WITH AIR GAP

Method of making a semiconductor device

Semiconductor device

Fabricating pillar solder bump

Semiconductor package and fabrication method thereof

Interconnect structure and method for forming the same

Semiconductor devices having through-electrodes and methods for fabricating the same

Redistribution structures for microfeature workpieces

IC embedded substrate and method of manufacturing the same

Placement of monolithic inter-tier vias (MIVs) within monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) using clustering to increase usable whitespace

Substrate-to-carrier adhesion without mechanical adhesion between abutting surfaces thereof

Word line coupling prevention using 3D integrated circuit

Method for forming recess-free interconnect structure

Methods for the production of microelectronic packages having radiofrequency stand-off layers

High speed differential wiring in glass ceramic MCMS

High speed differential wiring in glass ceramic MCMS

Method of fabricating semiconductor device

Apparatuses including scalable drivers and methods

SEMICONDUCTOR DEVICES

SEMICONDUCTOR DEVICE

Graphene and metal interconnects with reduced contact resistance

Semiconductor structure and semiconductor fabricating process for the same

Copper wire and dielectric with air gaps

Copper wire and dielectric with air gaps

Method of optical proximity correction for modifying line patterns and integrated circuits with line patterns modified by the same

LANDING STRUCTURE FOR THROUGH-SILICON VIA

Electronic device

Semiconductor device having metal patterns and piezoelectric patterns

Metal fuse structure for improved programming capability

Inter-level connection for multi-layer structures

Air gap formation by damascene process

Method of manufacturing a semiconductor device

Semiconductor module and method for manufacturing the same

Interconnect structure and method of forming same

Semiconductor package comprising a transistor chip module and a driver chip module and a method for fabricating the same

Method to etch Cu/Ta/TaN selectively using dilute aqueous HF/HSOsolution

METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES AND A SEMICONDUCTOR STRUCTURE

Low cost and ultra-thin chip on wafer on substrate (CoWoS) formation

Post passivation interconnect structures and methods for forming the same

SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

Semiconductor packaging device including via-in pad (VIP) and manufacturing method thereof

Via-fuse with low dielectric constant

Semiconductor structure and method for manufacturing the same

Inductor for semiconductor integrated circuit

Semiconductor device and method of fabricating the same

Structure and method for forming interconnect structure

Semiconductor package including a plurality of chips

Data storage device and methods of manufacturing the same

Semiconductor package having magnetic connection member

Package-on-package device

Integrated circuit structure with through-semiconductor via

Integrated circuit structure with metal cap and methods of fabrication

Bonding method using porosified surfaces for making stacked structures

Interconnection between inductor and metal-insulator-metal (MIM) capacitor

Inductive capacitive structure and method of making the same

Repairing monolithic stacked integrated circuits with a redundant layer and lithography process

Method of manufacturing semiconductor device

3-D package having plurality of substrates

Self-aligned nano-structures

Electronic device

Reliable passivation layers for semiconductor devices

Fabrication method of semiconductor device

Electro-migration enhancing method for self-forming barrier process in copper metalization

Semiconductor integrated device for display drive

Electronic chip with means of protecting its back face

Semiconductor device including fuse structure

Method of forming stacked trench contacts and structures formed thereby

Electronic system comprising stacked electronic devices comprising integrated-circuit chips

High aspect ratio vias for high performance devices

Semiconductor device with dual damascene wirings

Mechanism for forming patterned metal pad connected to multiple through silicon vias (TSVs)

Semiconductor device using Ge channel and manufacturing method thereof

E-fuses containing at least one underlying tungsten contact for programming

Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects

THROUGH-SILICON VIA STRUCTURE AND METHOD FOR IMPROVING BEOL DIELECTRIC PERFORMANCE

METHOD AND STRUCTURE OF FORMING BACKSIDE THROUGH SILICON VIA CONNECTIONS

Semiconductor device, manufacturing method thereof, and electronic apparatus

Power rail for preventing DC electromigration

Semiconductor devices having through-vias and methods for fabricating the same

Semiconductor device having dummy cell array

Semiconductor device and method for forming the same

Semiconductor memory apparatus for improving characteristics of power distribution network

PORE SEALING TECHNIQUES FOR POROUS LOW-K DIELECTRIC INTERCONNECT

Three-dimensional silicon structure for integrated circuits and cooling thereof

Semiconductor device having an inter-layer via (ILV), and method of making same

Contact structure and forming method

Clock skew adjusting method and structure

Connection member, semiconductor device, and stacked structure

Embedded semiconductor device package and method of manufacturing thereof

Devices Formed With Dual Damascene Process

Stacked microelectronic dice embedded in a microelectronic substrate

Semiconductor device

Landing pad in peripheral circuit for magnetic random access memory (MRAM)

Conductive ink for filling vias

Semiconductor device and manufacturing method for the same

Semiconductor device

Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device

DUMMY BARRIER LAYER FEATURES FOR PATTERNING OF SPARSELY DISTRIBUTED METAL FEATURES ON THE BARRIER WITH CMP

Interposer structure and manufacturing method thereof

Integrated circuit device packages and methods for manufacturing integrated circuit device packages

Semiconductor device

Electronic fuse having a substantially uniform thermal profile

Semiconductor device and manufacturing method thereof

Semiconductor package

Hybrid package transmission line circuits

Semiconductor devices and methods of forming same

Method for forming a packaged semiconductor device

PAD SOLUTIONS FOR RELIABLE BONDS

Semiconductor devices including insulating extension patterns between adjacent landing pads and methods of fabricating the same

Package structure having silicon through vias connected to ground potential

3D IC with serial gate MOS device, and method of making the 3D IC

Device with capped through-substrate via structure

Semiconductor device

Semiconductor arrangement, method for producing a semiconductor module, method for producing a semiconductor arrangement and method for operating a semiconductor arrangement

Interconnect structures and methods of forming same

Semiconductor devices having metal silicide layers and methods of manufacturing such semiconductor devices

PACKAGE INTERCONNECTS

Semiconductor device comprising capacitor and method of manufacturing the same

Method of manufacturing semiconductor device and semiconductor device

Semiconductor logic circuits fabricated using multi-layer structures

BEOL COMPATIBLE FET STRUCTURE

Semiconductor device and method for making same

SEMICONDUCTOR PACKAGE, METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE AND STACK TYPE SEMICONDUCTOR PACKAGE

Semiconductor device and method of manufacturing the same

Systems and methods to enhance passivation integrity

Semiconductor constructions and methods of forming electrically conductive contacts

Semiconductor module and a method for fabrication thereof by extended embedding technologies

Functional material

Method of providing a via hole and routing structure

Meander line resistor structure

Semiconductor devices with through via electrodes, methods of fabricating the same, memory cards including the same, and electronic systems including the same

Integrated circuit with a sidewall layer and an ultra-thick metal layer and method of making

Opening fill process and structure formed thereby

Packages with interposers and methods for forming the same

INTERPOSER WITH ELECTROSTATIC DISCHARGE PROTECTION

Semiconductor package having a baseplate with a die attach region and a peripheral region

Meander line resistor structure

Ultra high performance interposer

Semiconductor device and method of making wafer level chip scale package

Semiconductor device

Electronic fuse vias in interconnect structures

Redistribution board, electronic component and module

Semiconductor device having through-substrate vias

TFT array substrate and manufacturing method thereof, and display device

INDUCTIVE DEVICE THAT INCLUDES CONDUCTIVE VIA AND METAL LAYER

Semiconductor devices with enhanced electromigration performance

SPACER FOR ENHANCING VIA PATTERN OVERLAY TOLERENCE

Semiconductor device and manufacturing method thereof, and mounting method of semiconductor device

Profile control in interconnect structures

Semiconductor structures and fabrication methods for improving undercut between porous film and hardmask film

SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Modified via bottom for beol via efuse

SOC design with critical technology pitch alignment

Semiconductor device and manufacturing method thereof

SiCOH hardmask with graded transition layers

Semiconductor devices with close-packed via structures having in-plane routing and method of making same

Semiconductor package and method of manufacturing the semiconductor package

Active matrix using hybrid integrated circuit and bipolar transistor

Stacked package structure and method of forming a package-on-package device including an electromagnetic shielding layer

Chip package incorporating interfacial adhesion through conductor sputtering

Mechanisms for forming three-dimensional integrated circuit (3DIC) stacking structure

Semiconductor structure and method for making same

Capacitor in post-passivation structures and methods of forming the same

On-chip interconnects with reduced capacitance and method of fabrication thereof

Multiple via structure and method

Semiconductor device and manufacturing method of the same

MULTIPATTERNING VIA SHRINK METHOD USING ALD SPACER

Conductive line patterning

Reliable microstrip routing for electronics components

Semiconductor devices employing a barrier layer

CD control

TSV interconnect structure and manufacturing method thereof

Integration of optical components in integrated circuits

Semiconductor device and manufacturing method thereof

Method for filling trench with metal layer and semiconductor structure formed by using the same

Package with solder regions aligned to recesses

SEMICONDUCTOR DEVICE

Semiconductor device with internal substrate contact and method of production

Method and apparatus for back end of line semiconductor device processing

Self-aligned via interconnect using relaxed patterning exposure

Component, for example NMOS transistor, with active region with relaxed compression stresses, and fabrication method