Polymer layers embedded with metal pads for heat dissipation

Zero stand-off bonding system and method

Semiconductor device and a method increasing a resistance value of an electric fuse

Semiconductor device

Chip package and method for forming the same

Semiconductor device

Chip package and method thereof

Methods and apparatus of packaging semiconductor devices

Integrated circuit package

Single mask package apparatus

Method of forming package assembly

Semiconductor device

Semiconductor constructions having conductive lines which merge with one another

Pad structure exposed in an opening through multiple dielectric layers in BSI image sensor chips

Semiconductor device with post-passivation interconnect structure and method of forming the same

Semiconductor device

Chip package including recess in side edge

Semiconductor device with bump stop structure

Interconnect structure and method of fabricating same

Structure and method to determine through silicon via build integrity

Semiconductor device having a switch that expands and contracts by temperature change

Semiconductor package

Semiconductor device with a multiple nanowire channel structure and methods of variably connecting such nanowires for current density modulation

Integrated structure and method for fabricating the same

Semiconductor device and manufacturing method thereof

Metal PVD-free conducting structures

Anti-fuse of semiconductor device, semiconductor module and system each including the semiconductor device, and method for forming the anti-fuse

Fan out package structure and methods of forming

Mechanisms for forming post-passivation interconnect structure

Post passivation interconnect structures and methods for forming the same

Semiconductor device, method of manufacturing semiconductor device, and antenna switch module

Methods and apparatus of packaging semiconductor devices

Power semiconductor device including a cooling material

Repairing monolithic stacked integrated circuits with a redundant layer and lithography process

Semiconductor device having stacked memory elements and method of stacking memory elements on a semiconductor device

Semiconductor device with shielding layer in post-passivation interconnect structure

Semiconductor construct and manufacturing method thereof as well as semiconductor device and manufacturing method thereof

Contact pad for semiconductor devices

Semiconductor device and method of forming patterned repassivation openings between RDL and UBM to reduce adverse effects of electro-migration

Semiconductor device

Method for producing an electronic device with a disabled sensitive mode, and method for transforming such an electronic device to re-activate its sensitive mode

Semiconductor device having voids between top metal layers of metal interconnects

Interposer structure and manufacturing method thereof

ESD protection device

Interconnection structure with confinement layer

Semiconductor memory device

Crack stopping structure in wafer level packaging (WLP)

Compensating for warpage of a flip chip package by varying heights of a redistribution layer on an integrated circuit chip

Chip package and fabrication method thereof

Semiconductor device and method of making wafer level chip scale package

Stacked redistribution layers on die

Semiconductor device and manufacturing method thereof, and mounting method of semiconductor device

Chip package and fabrication method thereof

Semiconductor devices with close-packed via structures having in-plane routing and method of making same

Chip package incorporating interfacial adhesion through conductor sputtering

Capacitor in post-passivation structures and methods of forming the same

Semiconductor chip connecting semiconductor package

Semiconductor device having low dielectric insulating film and manufacturing method of the same

Semiconductor device and method for manufacturing the same

Integrated circuit structure and method for reducing polymer layer delamination

Polysilicon fuse, manufacturing method thereof, and semiconductor device including polysilicon fuse

Architecture of spare wiring structures for improved engineering change orders

Chip package and method for forming the same

Chip package

Semiconductor package and manufacturing method thereof

Chip package and method for forming the same

Chip package and method for forming the same

Microelectronic assembly including memory packages connected to circuit panel, the memory packages having stub minimization for wirebond assemblies without windows

Package structure and fabrication method thereof

Disabling electrical connections using pass-through 3D interconnects and associated systems and methods

High quality factor filter implemented in wafer level packaging (WLP) integrated device

Semiconductor device and method for manufacturing same

Package with passive devices and method of forming the same

Three-dimensional semiconductor architecture

Fan-out interconnect structure and method for forming same

Single mask package apparatus and method

WLCSP interconnect apparatus and method

Packaging devices, methods of manufacture thereof, and packaging methods

Methods and apparatus of packaging semiconductor devices

Line structure for repair and flat panel display device having the same

System and method for an improved interconnect structure

Ball amount process in the manufacturing of integrated circuit

Interconnect structures and methods of forming same

Directly sawing wafers covered with liquid molding compound

Microelectronic package with consolidated chip structures

Semiconductor construct and manufacturing method thereof as well as semiconductor device and manufacturing method thereof

Semiconductor device having stacked memory elements and method of stacking memory elements on a semiconductor device

Package with metal-insulator-metal capacitor and method of manufacturing the same

Device comprising nanostructures and method of manufacturing thereof

Methods and apparatus for transmission lines in packages

Semiconductor device including a phase change material

Semiconductor device and semiconductor module

Methods and apparatus of packaging of semiconductor devices

Semiconductor chip package and method for manufacturing thereof

Forming interconnect structures using pre-ink-printed sheets

Bumps for chip scale packaging including under bump metal structures with different diameters

Post-passivation interconnect structure and method of forming the same

Method and system for split threshold voltage programmable bitcells

Interconnect structure and forming method thereof

Method for manufacturing semiconductor device, semiconductor device and jig for forming wiring

Substrate with integrated passive devices and method of manufacturing the same

Flexible routing for chip on board applications

Semiconductor packaging structure and method for forming the same

Semiconductor IC packaging methods and structures

Semiconductor device with conductive vias

Compensating for warpage of a flip chip package by varying heights of a redistribution layer on an integrated circuit chip

Patterning methods and methods of forming electrically conductive lines

Stacked chip module with integrated circuit chips having integratable built-in self-maintenance blocks

Stacked chip module with integrated circuit chips having integratable and reconfigurable built-in self-maintenance blocks

Semiconductor package with bonding wires of reduced loop inductance

Method of fabricating a wafer level chip scale package without an encapsulated via

Through via structure and method

Post passivation interconnect structures and methods for forming the same

Semiconductor device having a fuse element

Semiconductor device having low dielectric insulating film and manufacturing method of the same

Electronic substrate, semiconductor device, and electronic device

Microelectronic packages having trench vias and methods for the manufacture thereof

Plating structure for wafer level packages

Structure to increase resistance to electromigration

Semiconductor package with improved redistribution layer design and fabricating method thereof

Metal pads with openings in integrated circuits

Methods and apparatus of packaging semiconductor devices

Semiconductor device, fabricating method thereof and semiconductor package including the semiconductor device

Semiconductor device and method of forming RDL using UV-cured conductive ink over wafer level package

Chip package

Semiconductor memory device

Semiconductor device including through via structures and redistribution structures

Method of making a semiconductor device having a post-passivation interconnect structure

Semiconductor device

Routing method for flip chip package and apparatus using the same

Semiconductor device and manufacturing method of same

Redistribution layer (RDL) with variable offset bumps

Method of forming post passivation interconnects

Anti-fuse of semiconductor device, semiconductor module and system each including the semiconductor device, and method for forming the anti-fuse

Semiconductor device and method for manufacturing the same

Package with passive devices and method of forming the same

Methods and apparatus of packaging semiconductor devices

Chip package and method for forming the same

Integrated circuit including wire structure, related method and design structure

Chip package and method for forming the same

Wafer-level package and method of manufacturing the same

Method and system for split threshold voltage programmable bitcells

Dual-side interconnected CMOS for stacked integrated circuits

Semiconductor package with stacked semiconductor chips

Through silicon via and method of forming the same

Thermally enhanced electronic package

Semiconductor device

Electrically erasable programmable non-volatile memory

Method for making a redistributed electronic device using a transferrable redistribution layer

Method for making a redistributed wafer using transferrable redistribution layers

Integrated Circuit Die And Method Of Fabricating

Microelectronic device having metal interconnection levels connected by programmable vias

Package assembly and method of forming the same

ESD protection device

Through silicon via and method of forming the same

Semiconductor package including stacked semiconductor chips and a redistribution layer

Methods of forming graphene-containing switches

Bump structure design for stress reduction

Post-passivation interconnect structure

Semiconductor device and method of forming patterned repassivation openings between RDL and UBM to reduce adverse effects of electro-migration

Under bump passive components in wafer level packaging

Methods and apparatus of under bump metallization in packaging semiconductor devices

WAFER LEVEL CHIP SIZE PACKAGE

Bumps for Chip Scale Packaging

Semiconductor device

Post-passivation interconnect structure and method of forming the same

Interposers for semiconductor devices and methods of manufacture thereof

Package on package devices and methods of packaging semiconductor dies

Semiconductor device having a fuse element

Wafer-level chip scale package with re-workable underfill

Post-passivation interconnect structure

Electrical connection for chip scale packaging

Stub minimization for wirebond assemblies without windows

Stub minimization for wirebond assemblies without windows

Stub minimization for wirebond assemblies without windows

FLASH MEMORY CARD WITHOUT A SUBSTRATE AND ITS FABRICATION METHOD

STACKED CHIP PACKAGE AND FABRICATION METHOD THEREOF

Thin film structure for high density inductors and redistribution in wafer level packaging

SEMICONDUCTOR DEVICE AND PROGRAMMING METHOD THEREOF

WAFER LEVEL PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Pad structure including glue layer and non-low-k dielectric layer in BSI image sensor chips

Methods of forming graphene-containing switches

WAFER LEVEL CHIP SCALE PACKAGE FOR WIRE-BONDING CONNECTION

Method and device for circuit routing by way of under-bump metallization

Forming wafer-level chip scale package structures with reduced number of seed layers

Methods of forming a metal pattern

Multi-layer interconnect structure for stacked dies

Semiconductor device and a method of manufacturing the same

Disabling electrical connections using pass-through 3D interconnects and associated systems and methods

Wiring switch designs based on a field effect device for reconfigurable interconnect paths

Uniformity control for IC passivation structure

Semiconductor component with a front side and a back side metallization layer and manufacturing method thereof

Chip package and package wafer with a recognition mark, and method for forming the same

Electrically Erasable Programmable Non-Volatile Memory

Wafer level package with thermal pad for higher power dissipation

Multi-die packages incorporating flip chip dies and associated packaging methods

Etchant and method for manufacturing semiconductor device using same

Mechanisms for forming copper pillar bumps using patterned anodes

Etchant and method for manufacturing semiconductor device using same

METHOD FOR CONTROLLING THE ELECTRICAL CONDUCTION BETWEEN TWO METALLIC PORTIONS AND ASSOCIATED DEVICE

Semiconductor device

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC SYSTEM USING THE SAME

Operating method of hardwired switch

Semiconductor device and method of manufacturing the same

Semiconductor device and method for manufacturing semiconductor device

Routing method for flip chip package and apparatus using the same

WAFER CHIP SCALE PACKAGE CONNECTION SCHEME

DEVICE MOUNTING BOARD AND METHOD OF MANUFACTURING THE SAME, SEMICONDUCTOR MODULE, AND MOBILE DEVICE

Integrated circuit package system with post-passivation interconnection and integration

Chip package and fabrication method thereof

Back side illuminated image sensor having isolated bonding pads

Semiconductor module having deflecting conductive layer over a spacer structure

Method and system for split threshold voltage programmable bitcells

Stacked structure of chips

Circuit substrate and method of manufacturing same

Manufacturing method of semiconductor device and semiconductor device

System of dynamic and end-user configurable electrical interconnects

Semiconductor device and method of forming conductive pillars in recessed region of peripheral area around the device for electrical interconnection to other devices

Flip chip device having simplified routing

Semiconductor package with a metal post and manufacturing method thereof

Self-organizing network with chip package having multiple interconnection configurations

Semiconductor device, fabricating method thereof and semiconductor package including the semiconductor device

Semiconductor chip including a chip via plug penetrating a substrate, a semiconductor stack, a semiconductor device package and an electronic apparatus including the semiconductor chip

Semiconductor package

Semiconductor package with bonding wires of reduced loop inductance

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Crack arrest vias for IC devices

Massively parallel interconnect fabric for complex semiconductor devices

Massively parallel interconnect fabric for complex semiconductor devices

Semiconductor device having pad structure with stress buffer layer

Compliant printed circuit wafer level semiconductor package

Semiconductor apparatus

Semiconductor device and electronic apparatus including the same

Mechanisms for forming copper pillar bumps using patterned anodes

Semiconductor device

Manufacturing method of semiconductor apparatus and semiconductor apparatus

Integrated circuit structure incorporating a conductor layer with both top surface and sidewall passivation and a method of forming the integrated circuit structure

Semiconductor device and method of designing a wiring of a semiconductor device

Semiconductor device and method of forming RDL wider than contact pad along first axis and narrower than contact pad along second axis

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SEMICONDUCTOR DEVICE

Multi-chip package module and a doped polysilicon trench for isolation and connection

Method for manufacture of integrated circuit package system with protected conductive layers for pads

Stress-engineered resistance-change memory device

Wafer level package (WLP) device having bump assemblies including a barrier metal

SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING THE SAME

Semiconductor device having a multilayer structure

Thermally enhanced electronic package

Semiconductor integrated circuit device and method of manufacturing the same

Thermally enhanced electronic package utilizing carbon nanocapsules and method of manufacturing the same

SEMICONDUCTOR SENSOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR SENSOR DEVICE, PACKAGE, METHOD OF MANUFACTURING PACKAGE, MODULE, METHOD OF MANUFACTURING MODULE, AND ELECTRONIC DEVICE

Semiconductor device

LASER PROCESSING WITH ORIENTED SUB-ARRAYS

Chip structure

Semiconductor device with grounding conductor film formed on upper surface of dielectric film formed above integrated circuit

Semiconductor integrated circuit having a multi-chip structure

SEMICONDUCTOR PACKAGE HAVING SIDE WALLS AND METHOD FOR MANUFACTURING THE SAME

Semiconductor chip, and semiconductor package and system each including the semiconductor chip

Chip package and method for forming the same

Forming interconnect structures using pre-ink-printed sheets

MICROELECTRONIC ASSEMBLIES HAVING COMPLIANCY

Semiconductor device having a fuse element

Method and system for split threshold voltage programmable bitcells

Positive-type photosensitive resin composition, method for producing resist pattern, semiconductor device, and electronic device

SEMICONDUCTOR DEVICE

Mask programmable interface selection

Dual-side interconnected CMOS for stacked integrated circuits

Multi-layer interconnect structure for stacked dies

Semiconductor device

Stacked chip package with redistribution lines

Semiconductor memory device

Semiconductor chip with coil element over passivation layer

CIRCUIT STRUCTURE OF AN ULTRA HIGH VOLTAGE LEVEL SHIFTER

Chip package and method for fabricating the same

Polysilicon resistor and E-fuse for integration with metal gate and high-k dielectric

Methods of forming a metal pattern and semiconductor device structure

Semiconductor die having a redistribution layer

Configurable memory sheet and package assembly

IC die including RDL capture pads with notch having bonding connectors or its UBM pad over the notch

Wafer level chip scale package without an encapsulated via

Method of fabricating a conductive post on an electrode

Semiconductor IC having electrical fuse capable of preventing thermal diffusion

Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board

Method of fabricating a 3-D device

Methods for forming through-substrate conductor filled vias, and electronic assemblies formed using such methods

Semiconductor device having a microcomputer chip mounted over a memory chip

Semiconductor apparatus capable of error revision using pin extension technique and design method therefor

Integrated circuit with pads connected by an under-bump metallization and method for production thereof

Method for manufacturing semiconductor device

Multi-chip stacked package and its mother chip to save interposer

INTERPOSER FILMS USEFUL IN SEMICONDUCTOR PACKAGING APPLICATIONS, AND METHODS RELATING THERETO

Redistribution layer enhancement to improve reliability of wafer level packaging

Semiconductor devices having redistribution structures and packages, and methods of forming the same

Semiconductor device including bottom surface wiring and manfacturing method of the semiconductor device

Post passivation interconnect with oxidation prevention layer

Microelectronic assemblies having compliant layers

Multi-Layer Connection Cell

Semiconductor module, method of manufacturing semiconductor module, and mobile device

Chip Stacking Device Having Re-Distribution Layer

Semiconductor package with pad parts electrically connected to bonding pads through re-distribution layers