207731 ⎘
Details of semiconductor or other solid state devices; Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
Sub-classes:Conductive Traces in Semiconductor Devices and Methods of Forming Same
#2POLYMER LAYERS EMBEDDED WITH METAL PADS FOR HEAT DISSIPATION
#3Interconnect Repair Multiplexing
#4INTEGRATED CIRCUIT WITH FAULT REPORTING STRUCTURE
#5THREE-DIMENSIONAL STACK OF HETEROGENEOUS MEMORY AND COMPUTE DIES
#6METHOD TO ENABLE LOGIC FOR FOCUSED ION BEAM CIRCUIT EDIT IN THE UPPERMOST ROUTING LAYERS
#7PASSIVATION SCHEME DESIGN FOR WAFER SINGULATION
#8BACK SIDE ILLUMINATED IMAGE SENSOR WITH REDUCED SIDEWALL-INDUCED LEAKAGE
#9SEMICONDUCTOR DEVICE INCLUDING VERTICAL ROUTING STRUCTURE AND METHOD FOR MANUFACURING THE SAME
#10METHODS OF FORMING SEMICONDUCTOR PACKAGES HAVING A DIE WITH AN ENCAPSULANT
#11Integrated circuit with fault reporting structure
#12Conductive Traces in Semiconductor Devices and Methods of Forming Same
#13BACKSIDE POWER WITH ON-DIE POWER SWITCHES
#14Techniques For Shifting Signal Transmission To Compensate For Defects In Pads In Integrated Circuits
#15POST PASSIVATION INTERCONNECT
#16METHOD OF MAKING SEMICONDUCTOR STRUCTURE INCLUDING BUFFER LAYER
#17Method of forming 3D stacked compute and memory with copper pillars
#18REDISTRIBUTION LAYER HAVING A SIDEVIEW ZIG-ZAG PROFILE
#19Passivation scheme design for wafer singulation
#20ANODIZED FILM SUBSTRATE BASE, ANODIZED FILM SUBSTRATE PART HAVING SAME, ANODIZED FILM-BASED INTERPOSER HAVING SAME, AND SEMICONDUCTOR PACKAGE HAVING SAME
#21Semiconductor device including vertical routing structure and method for manufacturing the same
#22Electronic device and method of fabricating an electronic device
#23Integrated circuit with fault reporting structure
#24Die-to-Die Power Delivery
#25Method of forming a 3D stacked compute and memory
#26Passivation scheme design for wafer singulation
#27Metal oxide layered structure and methods of forming the same
#28Semiconductor device having a dual material redistribution line
#29Polymer Layers Embedded with Metal Pads for Heat Dissipation
#30SEMICONDUCTOR DEVICE HAVING A REDISTRIBUTION LINE
#31Semiconductor packages having a die, an encapsulant, and a redistribution structure
#32Barrier structures between external electrical connectors
#33Semiconductor structure including buffer layer
#34Tunable coupler with coupling extension
#35Semiconductor device and method of manufacture
#36Post passivation interconnect
#37Integrated circuit structure and method for reducing polymer layer delamination
#38Integrated chip for standard logic performance improvement having a back-side through-substrate-via and method for forming the integrated chip
#39Passivation scheme design for wafer singulation
#40Horizontal programmable conducting bridges between conductive lines
#41Conductive traces in semiconductor devices and methods of forming same
#42Semiconductor element, manufacturing method of semiconductor element, and electronic apparatus
#43Semiconductor package and PoP type package
#44Back side illuminated image sensor with reduced sidewall-induced leakage
#45Semiconductor device including vertical routing structure and method for manufacturing the same
#46Method of forming semiconductor package transmission lines with micro-bump lines
#47Interconnect structure fabricated using lithographic and deposition processes
#48Method of forming semiconductor device having a dual material redistribution line and semiconductor device
#49Integrated electronic device with a redistribution region and a high resilience to mechanical stresses and method for its preparation
#50Horizontal programmable conducting bridges between conductive lines
#51Multi-dimensional vertical switching connections for connecting circuit elements
#52Interconnect structures and methods of forming same
#53Through via structure and method
#54Package with passive devices and method of forming the same
#55Fan-out interconnect structure and method for forming same
#56Transient voltage suppression device with thermal cutoff
#57Method of designing a layout, method of making a semiconductor structure and semiconductor structure
#58Artificial intelligence processor with three-dimensional stacked memory
#59Artificial intelligence processor with three-dimensional stacked memory
#60Apparatuses including redistribution layers and related microelectronic devices
#61Semiconductor device package and method of manufacturing the same
#62Metal oxide layered structure and methods of forming the same
#63Structure for standard logic performance improvement having a back-side through-substrate-via
#64Fabrication method of semiconductor package with stacked semiconductor chips
#65Semiconductor device and method of manufacture
#66Circuit for detecting damage to a peripheral edge on an integrated circuit die
#67Steep-switch field effect transistor with integrated bi-stable resistive system
#68Back side illuminated image sensor with reduced sidewall-induced leakage
#69Semiconductor device including vertical routing structure and method for manufacturing the same
#70Post-passivation interconnect structure
#71On-die termination (ODT) circuit configurable with via layer to support multiple standards
#72Phase-change material (PCM) RF switch with top metal contact to heating element
#73Phase-change material (PCM) RF switch having contacts to PCM and heating element
#74Phase-change material (PCM) RF switch with contacts to PCM and heating element
#75Method for fabricating contacts in a phase-change material (PCM) RF switch having a heating element
#76Programmable redistribution die
#77Integrated circuit (IC) structure for high performance and functional density
#78Dual silicide liner flow for enabling low contact resistance
#79Fabrication of contacts in an RF switch having a phase-change material (PCM) and a heating element
#80Post passivation interconnect
#81Integrated circuit (IC) structure for high performance and functional density
#82Post-passivation interconnect structure and method of forming the same
#83Semiconductor device and a method of increasing a resistance value of an electric fuse
#84Package with passive devices and method of forming the same
#85Barrier structures between external electrical connectors
#86Mechanisms for forming post-passivation interconnect structure
#87Reliable passivation for integrated circuits
#88Array substrate, fabricating method thereof, and display device
#89Apparatuses comprising semiconductor dies in face-to-face arrangements
#90Methods of forming semiconductor packages having a die with an encapsulant
#913D stack of electronic chips
#92RECONFIGURABLE INTERCONNECT ARRANGEMENTS USING THIN-FILM TRANSISTORS
#93Device comprising nanostructures and method of manufacturing thereof
#94Steep-switch field effect transistor with integrated bi-stable resistive system
#95Steep-switch field effect transistor with integrated bi-stable resistive system
#96Methods and apparatus for transmission lines in packages
#97Interconnect structures and methods of forming same
#98HARDWARE FALLBACK FOR NON-CONFIGURABLE FEATURES
#99Semiconductor structure and manufacturing method thereof
#100High reliability wafer level semiconductor packaging
#101Integrated circuit die having backside passive components and methods associated therewith
#102Anti-fuse device, memory device including the same and semiconductor device comprising an anti-fuse device
#103Three dimensional integrated circuit having redundant through silicon via base on rotatable cube
#104Reconfigurable RF Switch using Single or Multiple-Pole, Single or Multiple-Throw Switches
#105Integrated circuit package substrate
#106Package substrates with integral devices
#107Semiconductor device including vertical routing structure and method for manufacturing the same
#108Semiconductor device with post passivation structure
#109Semiconductor device, semiconductor chip, and test method for semiconductor chip
#110Semiconductor package having inductive lateral interconnects
#111Semiconductor devices and semiconductor packages including the same, and methods of manufacturing the semiconductor devices
#112Package assembly
#113Manufacturing method for semiconductor package including filling member and membrane member
#114Semiconductor devices including data storage patterns
#115Method and apparatus for forming backside die planar devices and saw filter
#116Semiconductor device structure comprising a plurality of metal oxide fibers and method for forming the same
#117Thrysitor and thermal switch device and assembly techniques therefor
#118Methods of manufacturing a multi-device package
#119Semiconductor integrated circuit having programmable logic device and resistive change elements
#120Wafer level package and capacitor
#121Post-passivation interconnect structure
#122Structure for standard logic performance improvement having a back-side through-substrate-via
#123Package structure of fingerprint identification chip
#124Polymer layers embedded with metal pads for heat dissipation
#125Microelectronic package including microelectronic elements having stub minimization for wirebond assemblies without windows
#126Semiconductor device and a corresponding method of manufacturing semiconductor devices
#127Semiconductor device and a corresponding method of manufacturing semiconductor devices
#128Integrated electronic device with a redistribution region and a high resilience to mechanical stresses and method for its preparation
#129Method of manufacturing a semiconductor device having redistribution layer including a dielectric layer made from a low-temperature cure polyimide
#130Method for manufacturing semiconductor devices
#131Apparatuses comprising semiconductor dies in face-to-face arrangements
#132System and method for an improved interconnect structure
#133Multi-device packages and related microelectronic devices
#134Post-passivation interconnect structure and method of forming the same
#135Metal oxide layered structure and methods of forming the same
#136Electrical device and a method for forming an electrical device
#137Package structure
#138Fan-out semiconductor package including electromagnetic interference shielding layer
#139Method of forming semiconductor device having a dual material redistribution line
#140Semiconductor device package and method of manufacturing the same
#141Fabrication method of semiconductor package with stacked semiconductor chips
#142SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
#143Semiconductor element, manufacturing method of semiconductor element, and electronic apparatus
#144Interconnect structures and methods of forming same
#145Thyristor and thermal switch device and assembly techniques therefor
#146Vanishing via for hardware IP protection from reverse engineering
#147Semiconductor device and its manufacturing method
#148Anti-fuse device and memory device including the same
#149Chip package
#150Post passivation interconnect and fabrication method therefor
#151Through via structure and method
#152SEMICONDUCTOR DEVICE AND A METHOD OF INCREASING A RESISTANCE VALUE OF AN ELECTRIC FUSE
#153Dielectric thermal conductor for passivating eFuse and metal resistor
#154Ring structures in device die
#155Semiconductor device and semiconductor package including the same
#156Package with passive devices and method of forming the same
#157High reliability wafer level semiconductor packaging
#158Semiconductor structure having a composite barrier layer
#159Activating reactions in integrated circuits through electrical discharge
#160Integrated circuit die having a split solder pad
#161Semiconductor device
#162Integrated circuit including wire structure, related method and design structure
#163Integrated circuit (IC) structure for high performance and functional density
#164Power control in integrated circuits
#165Package assembly
#166Device without zero mark layer
#167Electronic component device, method of mounting electronic component device on circuit board, and mounting structure of electronic component device on circuit board
#168Semiconductor device and semiconductor chip
#169Semiconductor device including conductive layer and conductive pillar disposed on conductive layer and method of manufacturing the same
#170Molded interconnect device, manufacturing method for molded interconnect device, and circuit module
#171Semiconductor constructions
#172Method of fabricating a post-passivation interconnect structure
#173Systems and methods to separate power domains in a processing device
#174ESD protection device
#175Semiconductor device, semiconductor chip, and test method for semiconductor chip
#176Semiconductor device and method of manufacture
#177Chip package and method for forming the same
#178Method of manufacturing semiconductor device
#179Semiconductor device and wafer level package including such semiconductor device
#180Interconnection structure with confinement layer
#181Microelectronic package including microelectronic elements having stub minimization for wirebond assemblies without windows
#182Methods and apparatus of packaging semiconductor devices
#183Semiconductor devices, multi-die packages, and methods of manufacure thereof
#184Barrier structures between external electrical connectors
#185Pad structure exposed in an opening through multiple dielectric layers in BSI image sensor chips
#186Integrated circuit die having backside passive components and methods associated therewith
#187Conductive traces in semiconductor devices and methods of forming same
#188Integrated circuit substrate and method for manufacturing the same
#189Integrated circuit substrate and method for manufacturing the same
#190Semiconductor device and method of making wafer level chip scale package
#191Reliable passivation for integrated circuits
#192Package structure and method for forming the same
#193Three-dimensional integrated circuit
#194Method of manufacturing semiconductor devices and corresponding device
#195Power overlay structure and reconstituted semiconductor wafer having wirebonds
#196Mechanisms for forming post-passivation interconnect structure
#197Semiconductor device and method
#198Semiconductor device structure comprising a plurality of metal oxide fibers and method for forming the same
#199Method of forming metal pads with openings in integrated circuits including forming a polymer extending into a metal pad
#200Integrated circuit structure and method for reducing polymer layer delamination
#201Dielectric thermal conductor for passivating eFuse and metal resistor
#202Back side illuminated image sensor with reduced sidewall-induced leakage
#203Structure for stacked logic performance improvement
#204Integrated circuit package substrate
#205Conductive paths through dielectric with a high aspect ratio for semiconductor devices
#206Method and apparatus for forming backside die planar devices and saw filter
#207Semiconductor device having repairable penetration electrode
#208Integrated circuit structure and method of forming the same
#209DUAL SILICIDE LINER FLOW FOR ENABLING LOW CONTACT RESISTANCE
#210Dual silicide liner flow for enabling low contact resistance
#211Integrated circuit package
#212Hybrid diffusion standard library cells, and related systems and methods
#213Semiconductor device, method of manufacturing semiconductor device, and antenna switch module
#214Package programmable decoupling capacitor array
#215Programmable resistive elements as variable tuning elements
#216Dielectric thermal conductor for passivating efuse and metal resistor
#217Semiconductor device
#218Method of packaging semiconductor devices
#219Semiconductor device and a method of increasing a resistance value of an electric fuse
#220Capacitor in post-passivation structures and methods of forming the same
#221Method of forming a semiconductor device with bump stop structure
#222Semiconductor element, manufacturing method of semiconductor element, and electronic apparatus
#223Multi-wafer stacking by Ox-Ox bonding
#224Semiconductor device and method of manufacturing the same
#225Staggered via redistribution layer (RDL) for a package and a method for forming the same
#226Methods of manufacturing a multi-device package
#227Packaging devices, methods of manufacture thereof, and packaging methods
#228Semiconductor structure with composite barrier layer under redistribution layer and manufacturing method thereof
#229Methods of forming multiple conductive features in semiconductor devices in a same formation process
#230Method of fabricating semiconductor device having voids between top metal layers of metal interconnects
#231Conductive traces in semiconductor devices and methods of forming same
#232Activating reactions in integrated circuits through electrical discharge
#233Chip package and method for fabricating the same
#234Interconnect structure and method of fabricating same
#235Semiconductor chip, flip chip package and wafer level package including the same
#236Fan-out interconnect structure and method for forming same
#237Microelectronic package having at least two microelectronic elements that are horizontally spaced apart from each other
#238Semiconductor device and wafer level package including such semiconductor device
#239Method of forming redistribution layer
#240Pad structure exposed in an opening through multiple dielectric layers in BSI image sensor chips
#241Method for fabricating package structure
#242Disabling electrical connections using pass-through 3D interconnects and associated systems and methods
#243Semiconductor device and manufacturing method of same
#244Metal oxide layered structure and methods of forming the same
#245Semiconductor device
#246Anti-fuse of semiconductor device, semiconductor module and system each including the semiconductor device, and method for forming the anti-fuse
#247Semiconductor device, fabricating method thereof and semiconductor package including the semiconductor device
#248Semiconductor device and method of manufacturing the same
#2493D package with through substrate vias
#250Semiconductor device
#251Device comprising a ductile layer and method of making the same
#252Multilayer structure for a semiconductor device and a method of forming a multilayer structure for a semiconductor device
#253Device without zero mark layer
#254Preservation of fine pitch redistribution lines
#255Semiconductor device and its manufacturing method
#256Monolithic stacked integrated circuits with a redundant layer for repairing defects
#257Activating reactions in integrated circuits through electrical discharge
#258Wiring structure for trench fuse component with methods of fabrication
#259Semiconductor devices, multi-die packages, and methods of manufacture thereof
#2603D integration of fanout wafer level packages
#261Electronic component and method for producing the same
#262Ball amount process in the manufacturing of integrated circuit
#263Chip package and method for forming the same
#264Chip package and manufacturing method thereof
#265Method of manufacturing semiconductor device
#266System and method for an improved interconnect structure
#267Semiconductor structure and manufacturing method thereof
#268Interconnect structures and methods of forming same
#269Repairing line structure and circuit repairing method using same
#270Package with metal-insulator-metal capacitor and method of manufacturing the same
#271Method of forming metal pads with openings in integrated circuits including forming a polymer plug extending into a metal pad
#272Transfer printing method
#273Power overlay structure having wirebonds and method of manufacturing same
#274Fan out package structure and methods of forming
#275Contact pad for semiconductor devices
#276Substrate structure and method of manufacturing the same
#277Wafer with liquid molding compound and post-passivation interconnect
#278Semiconductor package
#279Semiconductor device having a fuse element
#280Semiconductor devices with close-packed via structures having in-plane routing and method of making same
#281Back side illuminated image sensor having isolated bonding pads
#282Methods and apparatus for transmission lines in packages
#283Semiconductor device and manufacturing method thereof
#284Methods and apparatus of packaging semiconductor devices
#285Capacitor in post-passivation structures and methods of forming the same
#286Staggered via redistribution layer (RDL) for a package and a method for forming the same
#287ESD protection device
#288Microelectronic package with consolidated chip structures
#289Electrostatic discharge protection device
#290Through via structure
#291Three-dimensional semiconductor architecture
#292Semiconductor device having trench adjacent to receiving area and method of forming the same
#293Ring structures in device die
#2943DIC interconnect devices and methods of forming same
#295Semiconductor package device and forming the same
#296Electrostatic discharge diodes and methods of forming electrostatic discharge diodes
#297Method of forming post-passivation interconnect structure
#298Semiconductor device including a phase change material
#299Semiconductor device having low dielectric insulating film and manufacturing method of the same
#300Staggered power structure in a power distribution network (PDN)