Crack arrest vias for IC devices

Interconnect assemblies and methods of making and using same

Semiconductor device and method of forming wafer level ground plane and power ring

Structure, semiconductor structure and method of manufacturing a semiconductor structure and packaging thereof

Grounded seal ring structure in semiconductor devices

Substrateless power device packages

Integrated antennas in wafer level package

Semiconductor device and method of shielding semiconductor die from inter-device interference

Semiconductor device and method for manufacturing semiconductor device

Semiconductor device having a through electrode

LIGHT EMITTING DIODE PACKAGE STRUCTURE

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THROUGH ELECTRODE

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Simplified copper-copper bonding

METHOD FOR PACKAGING A SEMICONDUCTOR CHIP, AND SEMICONDUCTOR PACKAGE

Integrated circuits with backside metalization and production method thereof

Lead-free structures in a semiconductor device

Power/ground layout for chips

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

Integrated circuit package and physical layer interface arrangement

SEMICONDUCTOR DEVICE HAVING UNDER-BUMP METALLIZATION (UBM) STRUCTURE AND METHOD OF FORMING THE SAME

Semiconductor component having a second passivation layer having a first opening exposing a bond pad and a plurality of second openings exposing a top surface of an underlying first passivation layer

Bond pad for wafer and package for CMOS imager

Semiconductor device

Optoelectronic semiconductor component and method for producing an inorganic optoelectronic semiconductor component

Chip package

Light emitting device and method for manufacturing same

Incident radiation detector packaging

Process for realizing a connecting structure

Pass-through 3D interconnect for microelectronic dies and associated systems and methods

Method and structure for top metal formation of liquid crystal on silicon devices

Bump for semiconductor package, semiconductor package having bump, and stacked semiconductor package

Microelectronic assemblies having compliancy and methods therefor

Semiconductor device for semiconductor package having through silicon vias of different heights

Semiconductor chip having different pad width to UBM width ratios and method of manufacturing the same

Copper pillar bump with cobalt-containing sidewall protection

Under-bump metallization (UBM) structure and method of forming the same

Conductive pillar structure

Semiconductor die and method of forming noise absorbing regions between THVs in peripheral region of the die

Semiconductor package

Semiconductor device and method of manufacturing the same

Semiconductor device having plural insulated gate switching cells and method for designing the same

Pad structure having contact bars extending into substrate and wafer having the pad structure

Bonding apparatus and bonding method

Bonding apparatus

Method and system for forming conductive bumping with copper interconnection

Method of fabricating stacked chips in a semiconductor package

Semiconductor element having conductive vias and semiconductor package having a semiconductor element with conductive vias and method for making the same

Layered chip package and method of manufacturing same

Package systems having a eutectic bonding material and manufacturing methods thereof

Package systems having an opening in a substrate thereof and manufacturing methods thereof

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Semiconductor device and semiconductor package having the same

STACKED SEMICONDUCTOR PACKAGE HAVING CONDUCTIVE VIAS AND METHOD FOR MAKING THE SAME

CHIP STACKED STRUCTURE

MILLIMETER DEVICES ON AN INTEGRATED CIRCUIT

Methods of forming integrated circuits

Electronic component

Integrated circuit combination of a target integrated circuit and a plurality of photovoltaic cells connected thereto using the top conductive layer

Cost-effective TSV formation

Dimensionally decoupled ball limiting metalurgy

Flexible packaging for chip-on-chip and package-on-package technologies

Semiconductor device packages stacked together having a redistribution layer

Metal wiring structures for uniform current density in C4 balls

Method for producing a metallization having two multiple alternating metallization layers for at least one contact pad and semiconductor wafer having said metallization for at least one contact pad

Apparatus and method for uniform metal plating

Semiconductor device having a pad and plurality of interconnects

ESD DEVICE AND METHOD

Sheet-molded chip-scale package

Light emitting devices having roughened/reflective contacts and methods of fabricating same

Method of Contacting a Semiconductor Substrate

Semiconductor device manufacturing method using laser irradiation and dicing saw and semiconductor device thereof

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

FLIP-CHIP BONDING METHOD TO REDUCE VOIDS IN UNDERFILL MATERIAL

Manufacturing method of semiconductor device

Semiconductor device and method of bonding different size semiconductor die at the wafer level

Semiconductor device and method of forming TSV interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer

Semiconductor structure having metal oxide or nirtride passivation layer on fill layer and method for making same

Semiconductor structure and method for making same

SEMICONDUCTOR DEVICE PROVIDED WITH REAR PROTECTIVE FILM ON OTHER SIDE OF SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD OF THE SAME

Method and system for improving reliability of a semiconductor device

Semiconductor device

Semiconductor device and a method of manufacturing the same

Device and methods for electrostatic discharge protection

Semiconductor device and method of forming protective structure around semiconductor die for localized planarization of insulating layer

Organic light emitting display device and method of manufacturing the same

Stacked multi-die packages with impedance control

SEMICONDUCTOR PACKAGE AND METHOD FOR MAKING THE SAME

SEMICONDUCTOR DEVICE AND POWER SEMICONDUCTOR DEVICE

Semiconductor device and method for manufacturing the same

Stacked chip assembly having vertical vias

LAYER STACKS AND INTEGRATED CIRCUIT ARRANGEMENTS

Method for fabricating a neo-layer using stud bumped bare die

Printed circuit board having hexagonally aligned bump pads for substrate of semiconductor package, and semiconductor package including the same

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Wire bond through-via structure and method

Staged via formation from both sides of chip

Multi-function and shielded 3D interconnects

Substrate bonding with metal germanium silicon material

Semiconductor device with parasitic bipolar transistor

Vertical discrete devices with trench contacts and associated methods of manufacturing

Systems and methods for optimizing looping parameters and looping trajectories in the formation of wire loops

Method for reducing UBM undercut in metal bump structures

Copper bonding compatible bond pad structure and method

Method for packaging circuits

Apparatus for restricting moisture ingress

Semiconductor device and method of manufacturing the same

Semiconductor device and manufacturing method thereof

STACK PACKAGE AND METHOD FOR MANUFACTURING THE SAME

Die structure, die arrangement and method of processing a die

SEMICONDUCTOR CHIP, STACKED CHIP SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND FABRICATING METHOD THEREOF

Collar structure around solder balls that connect semiconductor die to semiconductor chip package substrate

SEMICONDUCTOR PACKAGE AND METHOD FOR MAKING THE SAME

Semiconductor device having metal posts non-overlapping with other devices and layout method of semiconductor device

Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in FO-WLCSP

Semiconductor device having pad structure with stress buffer layer

Semiconductor chip with redundant thru-silicon-vias

Semiconductor module and method for production thereof

3-D integrated semiconductor device comprising intermediate heat spreading capabilities

Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect

Power semiconductor chip package

Apparatus and method configured to lower thermal stresses

Programmable anti-fuse wire bond pads

Method for manufacturing semiconductor optical device

Layered chip package and method of manufacturing same

Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect

Die edge contacts for semiconductor devices

Semiconductor device with pads of enhanced moisture blocking ability

Semiconductor device and manufacturing method of semiconductor device

Embedded package and method for manufacturing the same

SEMICONDUCTOR DEVICE

Alignment marks in substrate having through-substrate via (TSV)

Semiconductor device and method of forming base leads from base substrate as standoff for stacking semiconductor die

Contacting means and method for contacting electrical components

Method of manufacturing semiconductor device

Interposer chip, multi-chip package including the interposer chip, and method of manufacturing the same

Bond pad for semiconductor die

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield and a method for fabricating the same

Manufacturing fixture for a ramp-stack chip package using solder for coupling a ramp component

Method and system for routing electrical connections of semiconductor chips

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

PACKAGE STRUCTURE HAVING THROUGH-SILICON-VIA (TSV) CHIP EMBEDDED THEREIN AND FABRICATION METHOD THEREOF

Semiconductor package

Bump structure with underbump metallization structure and integrated redistribution layer

Semiconductor apparatus

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

Pillar bumps and process for making same

Conductive connection structure with stress reduction arrangement for a semiconductor device, and related fabrication method

Semiconductor package structure and manufacturing process thereof

Semiconductor device, method for manufacturing same, and semiconductor apparatus

Method of manufacturing semiconductor package

Semiconductor module system having stacked components with encapsulated through wire interconnects (TWI)

Power and ground routing of integrated circuit devices with improved IR drop and chip performance

WAFER-LEVEL PACKAGE USING STUD BUMP COATED WITH SOLDER

Process for making conductive post with footing profile

Light emitting device and the manufacture method thereof

High-frequency switch

Thermal enhancement for multi-layer semiconductor stacks

Semiconductor device and method of forming Fo-WLCSP having conductive layers and conductive vias separated by polymer layers

Semiconductor device and method of forming B-stage conductive polymer over contact pads of semiconductor die in Fo-WLCSP

Semi-conductor chip with compressible contact structure and electronic package utilizing same

Seal ring structure with metal pad

Semiconductor device and method of producing same

Bond pad for low K dielectric materials and method for manufacture for semiconductor devices

SEMICONDUCTOR DEVICE

Process for chip capacitive coupling

WIREBONDING METHOD AND DEVICE ENABLING HIGH-SPEED REVERSE WEDGE BONDING OF WIRE BONDS

Three-dimensional integrated circuits with protection layers

Package substrate for bump on trace interconnection

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Semiconductor integrated circuit device

Semiconductor device

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Flip chip package utilizing trace bump trace interconnection

Flexible micro-system and fabrication method thereof

Package-on-package with fan-out WLCSP

Bottom source power MOSFET with substrateless and manufacturing method thereof

Optoelectronic semiconductor device

ELECTRONIC DEVICE MOUNTING STRUCTURE AND ELECTRONIC DEVICE MOUNTING METHOD

Alpha particle blocking wire structure and method fabricating same

Semiconductor apparatus, method of manufacturing the same, and method of manufacturing semiconductor package

Embedded wafer-level bonding approaches

ELECTRICAL OR ELECTRONIC COMPOSITE COMPONENT AND METHOD FOR PRODUCING AN ELECTRICAL OR ELECTRONIC COMPOSITE COMPONENT

Semiconductor device having a pad

Electronic device and method for production

Integrated circuit structure incorporating a conductor layer with both top surface and sidewall passivation and a method of forming the integrated circuit structure

Method of forming a memory device

Semiconductor device and method of designing a wiring of a semiconductor device

Semiconductor device and method of forming vertically offset bond on trace interconnects on different height traces

Semiconductor device

SEMICONDUCTOR PACKAGE

Microelectronic packages with nanoparticle joining

Laminated semiconductor wafer, laminated chip package and method of manufacturing the same

Laminated semiconductor wafer, laminated chip package and method of manufacturing the same

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

Fabricating process of circuit substrate and circuit substrate structure

Wafer level chip scale package

Power semiconductor device

Substrate bonding system and method of modifying the same

Forming low stress joints using thermal compress bonding

Tiered integrated circuit assembly and a method for manufacturing the same

Semiconductor device and method of forming RDL wider than contact pad along first axis and narrower than contact pad along second axis

Active chip on carrier or laminated chip having microelectronic element embedded therein

Methods of forming semiconductor elements using micro-abrasive particle stream

CONDUCTIVE STRUCTURE FOR A SEMICONDUCTOR INTEGRATED CIRCUIT

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Doping minor elements into metal bumps

Reducing delamination between an underfill and a buffer layer in a bond structure

Semiconductor device and method of forming RDL over contact pad with high alignment tolerance or reduced interconnect pitch

Chip scale package and fabrication method thereof

Microelectronic elements having metallic pads overlying vias

Microelectronic elements with rear contacts connected with via first or via middle structures

Metal-contamination-free through-substrate via structure

COATING AND ELECTRONIC COMPONENT

Method of manufacturing wafer level package

Method for manufacturing semiconductor devices having a metallisation layer

Layered chip package and method of manufacturing same

Layered chip package and method of manufacturing same

SEMICONDUCTOR DEVICE

Die package structure

Methods of forming bonded semiconductor structures using a temporary carrier having a weakened ion implant region for subsequent separation along the weakened region

Methods of forming bonded semiconductor structures

Conductive lines and pads and method of manufacturing thereof

BONDING PAD FOR ANTI-PEELING PROPERTY AND METHOD FOR FABRICATING THE SAME

Semiconductor device having an interconnect structure with TSV using encapsulant for structural support

Conductive sidewall for microbumps

Recessed pillar structure

Method for manufacturing semiconductor devices having a glass substrate

Semiconductor device and method of forming protective layer over exposed surfaces of semiconductor die

Substrate stand-offs for semiconductor devices

INTERCONNECTIONS FOR FLIP-CHIP USING LEAD-FREE SOLDERS AND HAVING REACTION BARRIER LAYERS

Solder bump with inner core pillar in semiconductor package

Wire bonding on reactive metal surfaces of a metallization of a semiconductor device by providing a protection layer

UBM Etching Methods

Semiconductor substrates with unitary vias and via terminals, and associated systems and methods

Wiring board and method for manufacturing the same

Multi-layer via structure

Backside processing of semiconductor devices

Methods, devices, and materials for metallization

SEMICONDUCTOR ELEMENT AND FABRICATION METHOD THEREOF

Microelectronic packages with dual or multiple-etched flip-chip connectors

Method of forming semiconductor die

Conductive pillar for semiconductor substrate and method of manufacture

High density chip stacked package, package-on-package and method of fabricating the same

IN-STREET DIE-TO-DIE INTERCONNECTS

Protecting bond pad for subsequent processing

Wiring board and method for manufacturing the same

Method for manufacture of integrated circuit package system with protected conductive layers for pads

Semiconductor package having a stacked structure

Internal packaging of a semiconductor device mounted on die pads

BUMPLESS BUILD-UP LAYER PACKAGE DESIGN WITH AN INTERPOSER

CORROSION-RESISTANT COPPER-TO-ALUMINUM BONDS

DOUBLE MOLDED CHIP SCALE PACKAGE

METHODS OF FORMING THROUGH-SILICON VIA STRUCTURES INCLUDING CONDUCTIVE PROTECTIVE LAYERS

Contact spring application to semiconductor devices

Wafer level package (WLP) device having bump assemblies including a barrier metal

Semiconductor arrangement, semiconductor module, and method for connecting a semiconductor chip to a ceramic substrate

Chip stack package

SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING THE SAME

Semiconductor device and method of forming RDL along sloped side surface of semiconductor die for z-direction interconnect

Semiconductor device having semiconductor substrate, and method of manufacturing the same

Protection film having a plurality of openings above an electrode pad

Semiconductor device and method of forming anisotropic conductive film between semiconductor die and build-up interconnect structure

Layered chip package and method of manufacturing same

MICROELECTRONIC PACKAGE AND METHOD OF MANUFACTURING SAME

Semiconductor element and method of manufacturing the semiconductor element

Semiconductor device

Laminated semiconductor substrate, laminated chip package and method of manufacturing the same

Manufacturing method for semiconductor devices

Stack package having reduced electrical connection length suitable for high speed operations and method of manufacturing the same

Stacked memory module and system

Electrode pad having a recessed portion

Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask

Semiconductor device having a multilayer structure

Multi-chip stack package structure

Multi-chip stack package structure

Multi-chip stack package structure

Integrated circuit system with recessed through silicon via pads and method of manufacture thereof

Plasma treatment for semiconductor devices

Power semiconductor device

High power and high temperature semiconductor power devices protected by non-uniform ballasted sources

Thermally enhanced electronic package

Lateral coupling enabled topside only dual-side testing of TSV die attached to package substrate

Semiconductor device

STACK-TYPE SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Semiconductor integrated circuit device and method of manufacturing the same

Semiconductor device with copper wire ball-bonded to electrode pad including buffer layer

Thermally enhanced electronic package utilizing carbon nanocapsules and method of manufacturing the same

ELECTRICALLY CONNECTING ROUTES OF SEMICONDUCTOR CHIP PACKAGE CONSOLIDATED IN DIE-ATTACHMENT

Semiconductor device and manufacturing method thereof

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF, WIRING BOARD AND MANUFACTURING METHOD THEREOF, SEMICONDUCTOR PACKAGE, AND ELECTRONIC APPARATUS

SEMICONDUCTOR CHIP WITH THROUGH ELECTRODES AND METHOD FOR MANUFACTURING THE SAME

WAFER LEVEL DIODE PACKAGE STRUCTURE

Passive integrated circuit

ELECTROSTATIC DISCHARGE PROTECTION SCHEME FOR SEMICONDUCTOR DEVICE STACKING PROCESS

Wafer level processing method and structure to manufacture semiconductor chip

Semiconductor device and method of manufacture thereof

Electronic device, resonator, oscillator and method for manufacturing electronic device

MOUNTING STRUCTURE, ELECTRONIC COMPONENT, CIRCUIT BOARD, BOARD ASSEMBLY, ELECTRONIC DEVICE, AND STRESS RELAXATION MEMBER