Semiconductor device

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Three-dimensional semiconductor architecture

SEMICONDUCTOR DEVICE

Hybrid molecular electronic devices containing molecule-functionalized surfaces for switching, memory, and sensor applications and methods for fabricating same

Devices and systems relating to a memory cell having a floating body

SOI radio frequency switch with enhanced electrical isolation

Semiconductor device and production method therefor

Semiconductor device with selected transistor properties

Semiconductor device and manufacturing method thereof

Reducing transistor junction capacitance by recessing drain and source regions

Replacement gate CMOS

Memory device having buried boosting plate and methods of operating the same

Integrated circuit using FinFETs and having a static random access memory (SRAM)

SOI (silicon on insulator) substrate improvements

Method for manufacturing SOI substrate

System for fabricating nanocoils using a wet etch technique

Semiconductor device and manufacturing methods with using non-planar type of transistors

Method for producing semiconductor chip, and field effect transistor and method for manufacturing same

Field effect transistors with vertically oriented gate electrodes and methods for fabricating the same

Strain engineering in semiconductor devices by using a piezoelectric material

Four-terminal gate-controlled LVBJTs

Semiconductor storage device

Semiconductor storage device

Method for fabricating a connection region in a semiconductor device

Production method for surrounding gate transistor semiconductor device

Methods of fabrication of semiconductor devices with low capacitance

Semiconductor device and production method therefor

Semiconductor field-effect transistor, memory cell and memory device

eDRAM memory cell structure and method of fabricating

Semiconductor structure

Semiconductor integrated circuit device and method of manufacturing the same

Method for making a substrate of the semiconductor on insulator type with an integrated ground plane

Body contacts for FET in SOI SRAM array

Solid-state image pick-up device and manufacturing method thereof, image-pickup apparatus, semiconductor device and manufacturing method thereof, and semiconductor substrate

SOI radio frequency switch with reduced signal distortion

Semiconductor device and semiconductor integrated circuit using the same

METHOD FOR TUNING THE THRESHOLD VOLTAGE OF A METAL GATE AND HIGH-K DEVICE

Semiconductor-on-insulator substrate and structure including multiple order radio frequency harmonic supressing region

CMOS semiconductor device

Heavy Ion Upset Hardened Floating Body SRAM Cells

Semiconductor surround gate SRAM storage device

Multiple crystallographic orientation semiconductor structures

SOI SUBSTRATE AND SEMICONDUCTOR DEVICE USING AN SOI SUBSTRATE

Reduction of thickness variations of a threshold semiconductor alloy by reducing patterning non-uniformities prior to depositing the semiconductor alloy

Increased depth of drain and source regions in complementary transistors by forming a deep drain and source region prior to a cavity etch

Embedded DRAM memory cell with additional patterning layer for improved strap formation

INTERLAYER DIELECTRIC UNDER STRESS FOR AN INTEGRATED CIRCUIT

Semiconductor integrated circuit device

Method To Create SOI Layer For 3D-Stacking Memory Array

METHOD TO INCREASE STRAIN ENHANCEMENT WITH SPACERLESS FET AND DUAL LINER PROCESS

Semiconductor device having switching element and method for fabricating semiconductor device having switching element

Semiconductor on insulator (SOI) device including a discharge path for a decoupling capacitor

Semiconductor memory device having a floating storage bulk region capable of holding/emitting excessive majority carriers

Semiconductor device and method of manufacturing the same

Method of fabricating hetero-junction bipolar transistor (HBT)

Receiving device including impedance control circuit and semiconductor device including impedance control circuit

Microelectromechanical systems structures and self-aligned high aspect-ratio combined poly and single-crystal silicon fabrication processes for producing same

LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH SUBSEQUENT SELF ALIGNED SHALLOW TRENCH ISOLATION

Semiconductor apparatus and method of manufacturing the semiconductor apparatus

Nonvolatile semiconductor memory device and method of manufacturing the same

Junction Field-Effect Transistor Having Insulator-Isolated Source/Drain Regions and Fabrication Method Therefor

SOI device with a buried insulating material having increased etch resistivity

Method of fabricating a semiconductor on insulator device having a frontside substrate contact

Metal High-K (MHK) Dual Gate Stress Engineering Using Hybrid Orientation (HOT) CMOS

Magnetoresistive memory cell using floating body effect, memory device having the same, and method of operating the memory device

SOI radio frequency switch with enhanced signal fidelity and electrical isolation

BIAS voltage generation circuit for an SOI radio frequency switch

SOI radio frequency switch for reducing high frequency harmonics

INTEGRATED MEMS AND IC SYSTEMS AND RELATED METHODS

Semiconductor device and method for manufacturing semiconductor device

Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Stacked non-volatile memory device and methods for fabricating the same

Method and structure for integrating capacitor-less memory cell with logic

Method for forming semiconductor devices with active silicon height variation

Anisotropic stress generation by stress-generating liners having a sublithographic width

Vertical floating body cell of a semiconductor device and method for fabricating the same

Memory device and manufacturing method the same

CMOS transistors with differential oxygen content high-K dielectrics

SOI substrates and SOI devices, and methods for forming the same

JFET device structures and methods for fabricating the same

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Multi-thickness semiconductor with fully depleted devices and photonic integration

Semiconductor device manufacturing method and semiconductor device

Semiconductor device and method for manufacturing the same

Semiconductor device with ESD protection function and ESD protection circuit

Method for reducing leakage current and increasing drive current in a metal-oxide semiconductor (MOS) transistor

Semiconductor devices and semiconductor device manufacturing methods

Depletion-type NAND flash memory

RESTRICTED STRESS REGIONS FORMED IN THE CONTACT LEVEL OF A SEMICONDUCTOR DEVICE

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

Recessed channel negative differential resistance-based memory cell

SEMICONDUCTOR-ON-INSULATOR (SOI) DEVICES USING VOID SPACES

Semiconductor Devices

Method for manufacturing semiconductor device

SEMICONDUCTOR DEVICES

Nonvolatile semiconductor memory device and manufacturing method thereof

Semiconductor device and method of manufacturing the same

High performance capacitors in planar back gates CMOS

CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials

Method of manufacturing semiconductor storage device

Semiconductor structure and method of forming the structure

SRAM DEVICE

SEMICONDUCTOR DEVICE

Semiconductor memory device

Method of forming a guard ring or contact to an SOI substrate

Recessed drain and source areas in combination with advanced silicide formation in transistors

Semiconductor Device and Method for Fabricating the Same

Ultrathin SOI CMOS devices employing differential STI liners

Semiconductor device with increased channel area and fabrication method thereof

Semiconductor device having buried insulation films and method of manufacturing the same

Semiconductor device with increased channel area

Manufacturing method of semiconductor device comprising silicide layer with varied thickness

SEMICONDUCTOR INTEGRATED CIRCUIT

Transistors, semiconductor memory cells having a transistor and methods of forming the same

Semiconductor device having controllable transistor threshold voltage

SOI substrate contact with extended silicide area

Capacitor-Less Dynamic Random Access Memory (DRAM) Devices

Layer transfer process and functionally enhanced integrated circuits produced thereby

Inverter, method of operating the same and logic circuit comprising inverter

eFuse and Resistor Structures and Method for Forming Same in Active Region

Semiconductor device comprising a buried poly resistor

ULTRA-THIN OXIDE BONDING FOR SI TO SI DUAL ORIENTATION BONDING

Semiconductor device with increased channel area and decreased leakage current

Asymmetric channel doping for improved memory operation for floating body cell (FBC) memory

Semiconductor devices including auxiliary gate electrodes and methods of fabricating the same

SOI device with more immunity from substrate voltage

Method for producing a thyristor

Semiconductor device

Method and system for monolithic integration of photonics and electronics in CMOS processes

Transistor, inverter including the same and methods of manufacturing transistor and inverter

Structured strained substrate for forming strained transistors with reduced thickness of active layer

Semiconductor device having vertical field effect transistor and method of manufacturing the same

Method of manufacturing semiconductor device over SOI substrate

Deep trench capacitor for SOI CMOS devices for soft error immunity

SOI MuGFETs having single gate electrode level

Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating

Logic switch and circuits utilizing the switch

Semiconductor device and methods for fabricating same

CMOS with channel P-FinFET and channel N-FinFET having different crystalline orientations and parallel fins

Method of producing a field effect transistor arrangement

INTEGRATING FABRICATION OF PHOTODETECTOR WITH FABRICATION OF CMOS DEVICE ON A SILICON-ON-INSULATOR SUBSTRATE

SEMICONDUCTOR DEVICE

Method of forming a high performance fet and a high voltage fet on a SOI substrate

Dynamic random access memory cell and manufacturing method thereof

Gate driving circuit

Implementing decoupling capacitors with hot-spot thermal reduction on integrated circuit chips

Semiconductor device including gate electrode having a laminate structure and plug electrically connected thereto

Area efficient 3D integration of low noise JFET and MOS in linear bipolar CMOS process

Component comprising a thin-film transistor and CMOS-transistors and methods for production

Performance enhancement in PMOS and NMOS transistors on the basis of silicon/carbon material

Transistor device and method of manufacturing such a transistor device

Lithographic process using a nanowire mask, and nanoscale devices fabricated using the process

Image sensor and manufacturing method thereof

Method for evaluating semiconductor wafer

Nonvolatile semiconductor memory device

Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same

Semiconductor device and fabrication method of the same

Implementing Reduced Hot-Spot Thermal Effects for SOI Circuits

Memory device

Three-dimensional silicon on oxide device isolation

CMOS image sensor including tunable read amplifier

High performance stress-enhance MOSFET and method of manufacture

ESD protection structures on SOI substrates

Localized biasing for silicon on insulator structures

Pin photodiode structure

Trench capacitor for high voltage processes and method of manufacturing the same

Backside illuminated image sensor with reduced dark current

Metal high-k transistor having silicon sidewall for reduced parasitic capacitance

Integration of a floating body memory on SOI with logic transistors on bulk substrate

High integrated semiconductor memory device

Dielectric layer above floating gate for reducing leakage current

Planar Metal-Insulator-Metal Circuit Element and Method for Planar Integration of Same

ELECTROSTATIC DISCHARGE PROTECTION DEVICE

TFT MONOS or SONOS memory cell structures

SEMICONDUCTOR DEVICE, INTEGRATED CIRCUIT, AND SEMICONDUCTOR MANUFACTURING METHOD

Semiconductor device

INTEGRATED CIRCUIT DEVICE, SYSTEM, AND METHOD OF FABRICATION

Semiconductor device reducing output capacitance due to parasitic capacitance

CMOS devices incorporating hybrid orientation technology (HOT) with embedded connectors

Bipolar junction transistor-based uncooled infrared sensor and manufacturing method thereof

Memory device and method for manufacturing the same

Memory device and method for manufacturing the same

Semiconductor device having buried oxide film

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SUBSTRATE

Strained-silicon-on-insulator single-and double-gate MOSFET and method for forming the same

Transistor and semiconductor device

Defect-free hybrid orientation technology for semiconductor devices

THIN SILICON SINGLE DIFFUSION FIELD EFFECT TRANSISTOR FOR ENHANCED DRIVE PERFORMANCE WITH STRESS FILM LINERS

ISOLATING BACK GATES OF FULLY DEPLETED SOI DEVICES

Compact multi-port cam cell implemented in 3D vertical integration

Semiconductor device

Integrated circuit chip with FETs having mixed body thicknesses and method of manufacture thereof

Structure and design structure having isolated back gates for fully depleted SOI devices

High density stable static random access memory

Switching device and testing apparatus

Method to reduce parastic capacitance in a metal high dielectric constant (MHK) transistor

Structures having lattice-mismatched single-crystalline semiconductor layers on the same lithographic level and methods of manufacturing the same

Bipolar transistor and back-gated transistor structure and method

Methods for fabricating SOI devices

Method of making wafer structure for backside illuminated color image sensor

Negative differential resistance device with high PVCR and fast switching speed and memory using the same

SRAM memory cell having transistors integrated at several levels and the threshold voltage VT of which is dynamically adjustable

Storage cell having a T-shaped gate electrode and method for manufacturing the same

Circuit with transistors integrated in three dimensions and having a dynamically adjustable threshold voltage VT

Capacitive sensor with stress relief that compensates for package stress

Stacked transistors and process

ULTRA-THIN SOI CMOS WITH RAISED EPITAXIAL SOURCE AND DRAIN AND EMBEDDED SIGE PFET EXTENSION

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

SOI deep trench capacitor employing a non-conformal inner spacer

Wafer For Backside Illumination Type Solid Imaging Device, Production Method Thereof And Backside Illumination Solid Imaging Device

Method for Making Transistors and the Device Thereof

Structure and method for buried inductors for ultra-high resistivity wafers for SOI/RF SiGe applications

CMOS DEVICE WITH METAL AND SILICIDE GATE ELECTRODES AND A METHOD FOR MAKING IT

Methods of fabricating a device structure for use as a memory cell in a non-volatile random access memory

SOI device with improved storage capacity and method for manufacturing the same

FinFETs having dielectric punch-through stoppers

Circuit and methods to improve the operation of SOI devices

Semiconductor substrate, semiconductor device, and method for manufacturing the semiconductor device

Transistor with high-k dielectric sidewall spacer

Structure and method for semiconductor power devices

Optical communication integration

Semiconductor device including a P-type field-effect transistor

Integrated circuit including a body transistor and method

Semiconductor array and method for manufacturing a semiconductor array

Semiconductor device with multi-trench separation region

P-channel germanium on insulator (GOI) one transistor memory cell

Semiconductor-on-insulator device structures with a body-to-substrate connection for enhanced electrostatic discharge protection, and design structures for such semiconductor-on-insulator device structures

Metallized conductive strap spacer for SOI deep trench capacitor

Structure and method for elimination of process-related defects in poly/metal plate capacitors

Semiconductor device and method for manufacturing same

Simultaneous buried strap and buried contact via formation for SOI deep trench capacitor

Circuit device

Method, structure and design structure for customizing history effects of SOI circuits

SOI TRANSISTOR WITH FLOATING BODY FOR INFORMATION STORAGE HAVING ASYMMETRIC DRAIN/SOURCE REGIONS

WAFER FOR BACKSIDE ILLUMINATION TYPE SOLID IMAGING DEVICE, PRODUCTION METHOD THEREOF AND BACKSIDE ILLUMINATION SOLID IMAGING DEVICE

Methods of forming lines of capacitorless one transistor DRAM cells, methods of patterning substrates, and methods of forming two conductive lines

Semiconductor device with cross-talk isolation using M-cap and method thereof

METHOD OF FABRICATING A SEMICONDUCTOR DEVICE

Hybrid orientation substrate with stress layer

Semiconductor structures with rare-earths

Three-dimensional memory devices and methods of manufacturing and operating the same

Semiconductor device

Field effect structure including carbon alloyed channel region and source/drain region not carbon alloyed

Charge breakdown avoidance for MIM elements in SOI base technology and method

SEMICONUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor Device Having a Floating Body Transistor and Method for Manufacturing the Same

Cell device and cell string for high density NAND flash memory

Semiconductor Device and Method for Manufacturing the Same

IC Substrate and Method of Manufacture of IC Substrate

Method and resultant structure for floating body memory on bulk wafer

Merged field effect transistor cells for switching

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Method of fabricating non-volatile memory device having separate charge trap patterns

Method of fabricating PMOS and NMOS transistor on the same substrate

Reduction of memory instability by local adaptation of re-crystallization conditions in a cache area of a semiconductor device

Semiconductor device comprising a metal gate stack of reduced height and method of forming the same

CMOS DEVICE COMPRISING AN NMOS TRANSISTOR WITH RECESSED DRAIN AND SOURCE AREAS AND A PMOS TRANSISTOR HAVING A SILICON/GERMANIUM MATERIAL IN THE DRAIN AND SOURCE AREAS

Modified hybrid orientation technology

SOI device having an increasing charge storage capacity of transistor bodies and method for manufacturing the same

SOI devices

TEMPERATURE MONITORING IN A SEMICONDUCTOR DEVICE BY USING AN PN JUNCTION BASED ON SILICON/GERMANIUM MATERIAL

Semiconductor chips having redistributed power/ground lines directly connected to power/ground lines of internal circuits and methods of fabricating the same

SOI field effect transistor with a back gate for modulating a floating body

Super hybrid SOI CMOS devices

Semiconductor devices and semiconductor apparatuses including the same

Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array

Semiconductor signal processing device

Hybrid orientation scheme for standard orthogonal circuits

Apparatus for using a well current source to effect a dynamic threshold voltage of a MOS transistor

Semiconductor device

Integrated circuit having memory cells including gate material having high work function, and method of manufacturing same

Semiconductor device having SOI structure

Method for forming a substrate contact for advanced SOI devices based on a deep trench capacitor configuration

Semiconductor device and method of manufacturing the same

Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same

SEMICONDUCTOR DEVICE USING ELEMENT ISOLATION REGION OF TRENCH ISOLATION STRUCTURE AND MANUFACTURING METHOD THEREOF

Method of creating a strained channel region in a transistor by deep implantation of strain-inducing species below the channel region

Vertical system integration

Semiconductor substrate, semiconductor device, and manufacturing methods for them

Capacitorless DRAM on bulk silicon

Solid-state image pickup element and solid-state image pickup device

Semiconductor memory device

Structure and method for improved SRAM interconnect

Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same

Anisotropic stress generation by stress-generating liners having a sublithographic width

SOI semiconductor components and methods for their fabrication

SEMICONDUCTOR DEVICE WITH AN SOI STRUCTURE

Semiconductor memory device and method for fabricating the same

SEMICONDUCTOR MEMORY DEVICE USING SILICON NITRIDE FILM AS CHARGE STORAGE LAYER OF STORAGE TRANSISTOR AND MANUFACTURING METHOD THEREOF

Silicon on insulator device and method for fabricating the same

Flash memory cell string

SOI BASED INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING

Methods of forming semiconductor devices having self-aligned bodies

Method and apparatus for fabricating a high-performance band-edge complementary metal-oxide-semiconductor device

Methods of designing an integrated circuit on corrugated substrate

Protection against charging damage in hybrid orientation transistors

Design structures for high-voltage integrated circuits