Hybrid orientation SOI substrates, and method for forming the same

SEMICONDUCTOR INTEGRATED CIRCUIT

Methods of forming semiconductor constructions

SHALLOW TRENCH ISOLATION FILL BY LIQUID PHASE DEPOSITION OF SiO2

Capacitor below the buried oxide of SOI CMOS technologies for protection against soft errors

Stressed SOI FET having tensile and compressive device regions

Semiconductor structure and method of forming the structure

Semiconductor device and method for manufacturing the same

Buried stress isolation for high-performance CMOS technology

SOI type semiconductor device having a protection circuit

One transistor DRAM device and method of forming the same

Silicon-on-insulator (“SOI”) transistor test structure for measuring body-effect

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor device with electrically floating body

Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain

Electronic device including insulating layers having different strains

Two-sided semiconductor-on-insulator structures and methods of manufacturing the same

Semiconductor storage device and manufacturing method thereof

SEMICONDUCTOR MEMORY DEVICE

Transistor with embedded silicon/germanium material on a strained semiconductor on insulator substrate

Non-volatile semiconductor memory based on enhanced gate oxide breakdown

MOSFET on SOI device

SEMICONDUCTOR DEVICE

CMOS devices having channel regions with a V-shaped trench and hybrid channel orientations, and method for forming the same

Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same

Subground rule STI fill for hot structure

Method of forming stressed SOI FET having doped glass box layer using sacrificial stressed layer

Non-volatile semiconductor memory and method for fabricating a non-volatile semiconductor memory

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Device selection circuitry constructed with nanotube ribbon technology

Integrated assist features for epitaxial growth bulk/SOI hybrid tiles with compensation

Integrated assist features for epitaxial growth bulk tiles with compensation

Electrically conductive path forming below barrier oxide layer and integrated circuit

Sub-lithographics opening for back contact or back gate

Semiconductor device

Wafer, semiconductor device, and fabrication methods therefor

Structure and method for MOSFET gate electrode landing pad

DYNAMIC RANDOM ACCESS MEMORY CELL AND MANUFACTURING METHOD THEREOF

Light erasable memory and method therefor

Structure and method for mobility enhanced MOSFETs with unalloyed silicide

Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same

Silicon-on-insulator chip with multiple crystal orientations

SIMULTANEOUSLY FORMING HIGH-SPEED AND LOW-POWER MEMORY DEVICES ON A SINGLE SUBSTRATE

Methods of forming semiconductor devices with extended active regions

Semiconductor device, method of controlling the same, and method of manufacturing the same

Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same

Soft error reduction of CMOS circuits on substrates with hybrid crystal orientation using buried recombination centers

Convex shaped thin-film transistor device

Method of combining floating body cell and logic transistors

Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same

Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same

Method for manufacturing a SOI substrate associating silicon based areas and GaAs based areas

Non-volatile memory device and method of operating the same

Method and resultant structure for floating body memory on bulk wafer

Semiconductor device including an active region and two layers having different stress characteristics

Semiconductor memory and manufacturing method thereof

Nonvolatile memory device and method of operating the same

Flash NAND memory cell array with charge storage elements positioned in trenches

Floating body memory cell having gates favoring different conductivity type regions

ID label, ID card, and ID tag

Crystal imprinting methods for fabricating substrates with thin active silicon layers

ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD OF FABRICATING SAME

Isolation spacer for thin SOI devices

SEMICONDUCTOR INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREFOR

Isolated multigate FET circuit blocks with different ground potentials

Isolation spacer for thin SOI devices

Floating body memory and method of fabricating the same

SEMICONDUCTOR DEVICE STRUCTURE WITH ACTIVE REGIONS HAVING DIFFERENT SURFACE DIRECTIONS

NMOS device, PMOS device, and SiGe HBT device formed on SOI substrate and method of fabricating the same

Method for fabricating SOI device

Semiconductor memory device

Semiconductor storage unit, semiconductor device and display device as well as liquid crystal display and image receiving apparatus

Device patterned with sub-lithographic features with variable widths

Semiconductor device and manufacturing method thereof

Integrated circuit having a top side wafer contact and a method of manufacture therefor

Semiconductor device

Semiconductor Device and Manufacturing Method Thereof

Dual wired integrated circuit chips

Semiconductor device

Semiconductor device and manufacturing method thereof

Semiconductor device fabrication method and semiconductor device

Semiconductor substrate including a plurality of insulating regions, semiconductor device having the same, and method of manufacturing the device

Semiconductor device formed on (111) surface of a Si crystal and fabrication process thereof

Methods for forming III-V semiconductor device structures

Process of forming an electronic device including a conductive structure extending through a buried insulating layer

Methods of forming vertical transistors

CMOS device with metal and silicide gate electrodes and a method for making it

Reducing Crystal Defects from Hybrid Orientation Technology During Semiconductor Manufacture

Electronic device including a conductive structure extending through a buried insulating layer

SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

TRANSISTOR HAVING SOURCE/DRAIN REGION ONLY UNDER SIDEWALL SPACER EXCEPT FOR CONTACTS AND METHOD

Memory device and semiconductor device

Semiconductor device, logic circuit and electronic equipment

CMOS structure including topographic active region

Method of fabricating a stressed MOSFET by bending SOI region

Method of enhancing hole mobility

Method of fabricating a semiconductor device

Method of fabricating a semiconductor device

Hybrid orientation substrate and method for fabrication of thereof

Integration of a floating body memory on SOI with logic transistors on bulk substrate

HYBRID CRYSTALLOGRAPHIC SURFACE ORIENTATION SUBSTRATE HAVING ONE OR MORE SOI REGIONS AND/OR BULK SEMICONDUCTOR REGIONS

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

Nonvolatile semiconductor memory device and method for manufacturing the same

Electronic device including a heterojunction region

Method of providing protection against charging damage in hybrid orientation transistors

Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers

Process charging and electrostatic damage protection in silicon-on-insulator technology

Non-volatile memory device having separate charge trap patterns and method of fabricating the same

FET Channel Having a Strained Lattice Structure Along Multiple Surfaces

FET Channel Having a Strained Lattice Structure Along Multiple Surfaces

Phosphorous doping methods of manufacturing field effect transistors having multiple stacked channels

Method of fabricating vertical body-contacted SOI transistor

SOI BIPOLAR TRANSISTORS WITH REDUCED SELF HEATING

MULTIPLE LAYER AND CRYSTAL PLANE ORIENTATION SEMICONDUCTOR SUBSTRATE

Integrated circuits

Multiple layer and crystal plane orientation semiconductor substrate

Ultra-thin oxide bonding for S1 to S1 dual orientation bonding

Anodization

Semiconductor device and fabrication method thereof

Method of forming an implantable electronic device chip level hermetic and biocompatible electronics package using SOI wafers

Semiconductor device and method for fabricating a semiconductor device

Decoder for a stationary switch machine

Vertical channel transistor structure and manufacturing method thereof

Dual work-function single gate stack

Semiconductor structures including multiple crystallographic orientations and methods for fabrication thereof

DUAL-GATE MEMORY DEVICE AND OPTIMIZATION OF ELECTRICAL INTERACTION BETWEEN FRONT AND BACK GATES TO ENABLE SCALING

Self-aligned strap for embedded trench memory on hybrid orientation substrate

MOS transistor on an SOI substrate with a body contact and a gate insulating film with variable thickness

Memory devices and memory systems having the same

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SOI semiconductor components and methods for their fabrication

Bottom-gate sonos-type cell having a silicide gate

Transistor surround gate structure with silicon-on-insulator isolation for memory cells, memory arrays, memory devices and systems and methods of forming same

Strained Si/SiGe/SOI islands and processes of making same

High-voltage MOS device improvement by forming implantation regions

Semiconductor device

Semiconductor memory and method for manufacturing a semiconductor memory

Method of fabricating a semiconductor device

Integrated circuit having a drive circuit

Semiconductor device

Semiconductor memory device and semiconductor integrated circuit

Electronically scannable multiplexing device

Method of fabricating a semiconductor device

Insulated-gate field-effect thin film transistors

Semiconductor device

Semiconductor device and manufacturing method of the same

Method for producing multi-gate field-effect transistor with fin structure having drain-extended MOS field-effect transistor

SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME

Structures and methods for manufacturing of dislocation free stressed channels in bulk silicon and SOI CMOS devices by gate stress engineering with SiGe and/or Si:C

Vertical SOI transistor memory cell and method of forming the same

CMOS devices incorporating hybrid orientation technology (HOT) with embedded connectors

Strained-channel fin field effect transistor (FET) with a uniform channel thickness and separate gates

Variable Threshold Transistor For The Schottky FPGA And Multilevel Storage Cell Flash Arrays

Apparatus and methods for multi-gate silicon-on-insulator transistors

Semiconductor device

Examination apparatus for biological sample and chemical sample

Strained-channel fin field effect transistor (FET) with a uniform channel thickness and separate gates

SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME

Method for fabricating semiconductor device

Semiconductor device

Method of manufacturing semiconductor device having impurity region under isolation region

Semiconductor apparatus having a semicondutor element with a high dielectric constant film

SEMICONDUCTOR DEVICE HAVING CMOS DEVICE

THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURE AND METHOD FOR FABRICATION THEREOF

Semiconductor structure with enhanced performance using a simplified dual stress liner configuration

Electrically erasable and programmable read only memory device comprising common source region and method of manufacturing same

Method of fabricating a semiconductor device

Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same

Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates

Semiconductor structures with body contacts and fabrication methods thereof

Method of manufacturing semiconductor device having impurity region under isolation region

Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same

Buried decoupling capacitors, devices and systems including same, and methods of fabrication

Trench isolated capacitive micromachined ultrasonic transducer arrays with a supporting frame

Element formation substrate, method of manufacturing the same, and semiconductor device

Body-contacted semiconductor structures and methods of fabricating such body-contacted semiconductor structures

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Semiconductor system using germanium condensation

THREE DIMENSIONAL INTEGRATED CIRCUIT AND METHOD OF DESIGN

Ballistic direct injection NROM cell on strained silicon structures

Semiconductor device and method for manufacturing the same

VARIABLE THRESHOLD TRANSISTOR FOR THE SCHOTTKY FPGA AND MULTILEVEL STORAGE CELL FLASH ARRAYS

SEMICONDUCTOR DEVICE

Semiconductor device and method of fabricating semiconductor device

Pseudo SOI substrate and associated semiconductor devices

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

INTEGRATED CIRCUIT (IC) WITH HIGH-Q ON-CHIP DISCRETE CAPACITORS

Integrated circuit with metal heat flow path coupled to transistor and method for manufacturing such circuit

Programmable random logic arrays using PN isolation

Semiconductor device with fin-type field effect transistor and manufacturing method thereof.

Selective silicon-on-insulator isolation structure and method

Semiconductor-on-insulator (SOI) strained active area transistor

Display device using light-emitting element

Semiconductor method and device with mixed orientation substrate

INTEGRATED CIRCUIT CHIP WITH FETS HAVING MIXED BODY THICKNESSES AND METHOD OF MANUFACTURE THEREOF

Semiconductor memory device and manufacturing method of the same

Semiconductor memory device and manufacturing method of the same

Memory element and semiconductor device

Method of manufacturing a semiconductor device and a non-volatile semiconductor storage device including the formation of an insulating layer using a plasma treatment

Process for controlling performance characteristics of a negative differential resistance (NDR) device

Twisted dual-substrate orientation (DSO) substrates

Front-rear contacts of electronics devices with induced defects to increase conductivity thereof

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SOI device and method for its fabrication

Vertical-type, integrated bipolar device and manufacturing process thereof

Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX)

Selective uniaxial stress modification for use with strained silicon on insulator integrated circuit

Semiconductor component including an isolation structure and a contact to the substrate

Semiconductor device formed in semiconductor layer arranged on substrate with one of insulating film and cavity interposed between the substrate and the semiconductor layer

Semiconductor device to suppress leak current at an end of an isolation film

Test structure for determining characteristics of semiconductor alloys in SOI transistors by x-ray diffraction

SOI Device with charging protection and methods of making same

Capacitorless one transistor DRAM cell, integrated circuitry comprising an array of capacitorless one transistor DRAM cells, and method of forming lines of capacitorless one transistor DRAM cells

Dynamic random access memory with an amplified capacitor

Hybrid crystal orientation CMOS structure for adaptive well biasing and for power and performance enhancement

Method for fabricating a localize SOI in bulk silicon substrate including changing first trenches formed in the substrate into unclosed empty space by applying heat treatment

Selective formation of stress memorization layer

Semiconductor device and driving method therefor

Controlling output current delivered by a transistor

Semiconductor memory device and method of manufacturing the same

Method of making metal gate transistors

SOI devices and methods for fabricating the same

Silicon-on-insulator (SOI) junction field effect transistor and method of manufacture

CMOS devices with stressed channel regions, and methods for fabricating the same

Semiconductor device fabrication method

Epitaxy silicon on insulator (ESOI)

SILICON-ON-INSULATOR (SOI) MEMORY DEVICE

Semiconductor device including a capacitance

Backside contacts for MOS devices

Forward body bias-controlled semiconductor integrated circuit

Protect diodes for hybrid-orientation substrate structures

Method of fabricating heterojunction photodiodes with CMOS

SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME

Nonvolatile semiconductor memory device

MULTIPLE DIELECTRIC FINFET STRUCTURE AND METHOD

Method for producing a semiconductor arrangement, semiconductor arrangement and its application

Semiconductor memory device and method of manufacturing the same

Method for producing SiGebased zones with different contents in Ge on a same substrate by condensation of germanium

Bipolar transistor, BiCMOS device, and method for fabricating thereof

Three dimensional integrated circuit and method of design

Memory array having a programmable word length, and method of operating same

Semiconductor memory device and method of manufacturing the same

Curled semiconductor transistor

Method for producing SiGebased zones with different contents in Ge on a same substrate by condensation of germanium

Semiconductor device and manufacturing method of the same

SEMICONDUCTOR CIRCUIT ARRANGEMENT AND ASSOCIATED METHOD FOR TEMPERATURE DETECTION

Heating element for microfluidic and micromechanical applications

Dual surface SOI by lateral epitaxial overgrowth

Semiconductor device and manufacturing method thereof

Semiconductor integrated circuit devices having high-Q wafer back-side capacitors

CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials

STRUCTURE AND METHOD FOR IMPLEMENTING OXIDE LEAKAGE BASED VOLTAGE DIVIDER NETWORK FOR INTEGRATED CIRCUIT DEVICES

Asymmetric channel doping for improved memory operation for floating body cell (FBC) memory

Nonvolatile semiconductor memory device

Integrated Circuit with a Transistor Structure Element

Semiconductor device and method of manufacturing same

Capacitor below the buried oxide of SOI CMOS technologies for protection against soft errors

Electronic devices including a semiconductor layer

Semiconductor device having multi-gate structure and method of manufacturing the same

Structure and method of fabricating a hybrid substrate for high-performance hybrid-orientation silicon-on-insulator CMOS devices

ESD protection element

Dual wired integrated circuit chips

Silicon-on-insulator structures

Hybrid strained orientated substrates and devices

Method and system for reducing charge damage in silicon-on-insulator technology

Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors

Semiconductor memory device

Semiconductor device having a frontside contact and vertical trench isolation and method of fabricating same

LOCOS on SOI and HOT semiconductor device and method for manufacturing

Selective uniaxial stress relaxation by layout optimization in strained silicon on insulator integrated circuit

Semiconductor device and method of manufacturing the same

SOI SUBSTRATE AND SEMICONDUCTOR INTEGRATED CIRUIT DEVICE

Semiconductor device and method for manufacturing semiconductor device

Method of making wafer structure for backside illuminated color image sensor

Strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels

Electrostatic discharge protection device and method of fabricating same

Structure Having Isolation Structure Including Deuterium Within A Substrate And Related Method

Method of forming transistor structure having stressed regions of opposite types

Methods and apparatus for implementing bit-by-bit erase of a flash memory device

Semiconductor device

Hybrid Transistor Structure and a Method for Making the Same

Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors

Integrated circuit chip with FETs having mixed body thickness and method of manufacture thereof

Semiconductor memory device including an SOI substrate

SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES AND SEMICONDUCTOR DEVICES USING VOID SPACES

Body-tied MOSFET device with strained active area

Semiconductor Device and Method for Manufacturing the Same

Semiconductor device having stressed etch stop layers of different intrinsic stress in combination with PN junctions of different design in different device regions

Method for fabricating semiconductor

Method of manufacturing a semiconductor integrated circuit and semiconductor integrated circuit

High performance stress-enhance MOSFET and method of manufacture

High performance stress-enhance MOSFET and method of manufacture

Structure and method for implementing oxide leakage based voltage divider network for integrated circuit devices

Hybrid orientation SOI substrates, and method for forming the same

Semiconductor element, semiconductor device and methods for manufacturing thereof

SOI transistor having a reduced body potential and a method of forming the same

Patterning sub-lithographic features with variable widths

Method for fabricating a semiconductor component including a high capacitance per unit area capacitor

Method of forming silicon-on-insulator wafer having reentrant shape dielectric trenches

CONDUCTIVE SPACERS FOR SEMICONDUCTOR DEVICES AND METHODS OF FORMING