Semiconductor integrated circuit device and semiconductor memory using the same

Semiconductor integrated circuit device and sense amplifier of memory

Double silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) structures

Vertically wired integrated circuit and method of fabrication

Semiconductor memory device and method of manufacturing the same

Non-volatile semiconductor memory with single layer gate structure

Semiconductor device and semiconductor memory using the same

Fully depleted silicon-on-insulator CMOS logic

Static random access memories including a silicon-on-insulator substrate

Shallow trench isolation (STI) region with high-K liner and method of formation

High-density split-gate FinFET

TFT mask ROM and method for making same

Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers

Trench capacitor DRAM cell using buried oxide as array top oxide

Silicide proximity structures for CMOS device performance improvements

Capacitorless 1-transistor DRAM cell and fabrication method

High performance voltage control diffusion resistor

Semiconductor over-voltage protection structure for integrated circuit and for diode

Semiconductor device

Processes of forming stacked resistor constructions

Silicon on insulator device and layout method of the same

MOSFET performance improvement using deformation in SOI structure

Nanotube films and articles

Semiconductor-on-insulator constructions

Semiconductor device including transistors having different drain breakdown voltages on a single substrate

High breakdown voltage junction terminating structure

Semiconductor-on-insulator constructions

Fully-depleted castellated gate MOSFET device and method of manufacture thereof

Double gate field effect transistor and method of manufacturing the same

Display device using electroluminescence material

Solution to thermal budget

Ultra thin channel MOSFET

Methods of forming devices, constructions and systems comprising thyristors

Sealing gasket with flexible stopper

Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientations

Bipolar/thin film SOI CMOS structure and method of making same

Computer systems containing resistors which include doped silicon/germanium

Semiconductor device including first and second transistor groups and semiconductor integrated circuit device

Semiconductor device having epitaxial layer

Heterojunction bipolar transistor with monolithically integrated junction field effect transistor and method of manufacturing same

Semiconductor device having electrical contact from opposite sides including a via with an end formed at a bottom surface of the diffusion region

Semiconductor device having silicon on insulator structure and method of fabricating the same

Silicon on insulator device and layout method of the same

Integrated semiconductor storage with at least a storage cell and procedure

Resistor with reduced leakage

CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture

SOI type MOSFET

Stress inducing spacers

Semiconductor memory device and method for fabricating the same

Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates

EMI and noise shielding for multi-metal layer high frequency integrated circuit processes

Method of manufacturing semiconductor device having trench isolation

Semiconductor diode with reduced leakage

Localized biasing for silicon on insulator structures

Semiconductor element and process for manufacturing the same

Strained Si/SiGe/SOI islands and processes of making same

Varying carrier mobility in semiconductor devices to achieve overall design goals

Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions

Method and structure for buried circuits and devices

Silicon-on-insulator device structure

Method and apparatus for providing an integrated active region on silicon-on-insulator devices

Method using quasi-planar double gated fin field effect transistor process for the fabrication of a thyristor-based static read/write random-access memory

Vertical system integration

Stabilization in device characteristics of a bipolar transistor that is included in a semiconductor device with a CMOSFET

Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors

Semiconductor element and semiconductor memory device using the same

Stable PD-SOI devices and methods

Ultra-thin semiconductors bonded on glass substrates

Semiconductor device and method for manufacturing partial SOI substrates

Electronic systems comprising memory devices

Semiconductor device and method of fabricating the same

Stable PD-SOI devices and methods

Fabrication of silicon-on-nothing (SON) MOSFET fabrication using selective etching of SiGelayer

SOI device with reduced drain induced barrier lowering

Method for converting a planar transistor design to a vertical double gate transistor design

Semiconductor chip having multiple functional blocks integrated in a single chip and method for fabricating the same

FET channel having a strained lattice structure along multiple surfaces

Field effect transistor and method of manufacturing the same

Semiconductor element, semiconductor device and methods for manufacturing thereof

Capacitor that includes high permittivity capacitor dielectric

Semiconductor device and method for manufacturing the same

CaF2 lenses with reduced birefringence

Method for fabricating semiconductor device

Coiled circuit device and method of making the same

Semiconductor substrate and manufacturing process therefor

Semiconductor device

Damascene gate multi-mesa MOSFET

GATE LENGTH PROXIMITY CORRECTED DEVICE

Semiconductor apparatus having first and second gate electrodes

Method of fabricating a semiconductor device

Silicon-on-insulator (SOI) integrated circuit (IC) chip with the silicon layers consisting of regions of different thickness

Radiation-hardened silicon-on-insulator CMOS device, and method of making the same

Semiconductor device with an enhancement type field effect transistor in which threshold voltage is dependent upon substrate bias voltage

Method for making a system for selecting one wire from a plurality of wires

SRAM cell

Methods of fabricating double-sided hemispherical silicon grain electrodes and capacitor modules

Multi-configurable independently multi-gated MOSFET

Integrated circuit having pairs of parallel complementary FinFETs

Thin film memory, array, and operation method and manufacture method therefor

Semiconductor memory device including an SOI substrate

High-performance one-transistor memory cell

Double-gated transistor circuit

Method of fabricating semiconductor side wall fin

Methods for producing a 3D semiconductor memory device and structure

3D semiconductor device and structure with transistors

3D semiconductor device and structure with oxide bonds

Monolithic multi-FETs

Integrated circuit with active region jogs

Structure with polycrystalline isolation region below polycrystalline fill shape(s) and selective active device(s), and related method

Analog-to-digital inverter circuit structure with FDSOI transistors

High density IC capacitor structure

SOI devices with air gaps and stressing layers

Efficient heat-sinking in PIN diode

Simplified bias scheme for digital designs

Devices with slotted active regions

Dynamic substrate biasing for extended voltage operation

Vertically stacked transistors

Formation of stacked nanosheet semiconductor devices

Formation of semiconductor devices with dual trench isolations

Multiple work function nanosheet field-effect transistors with differential interfacial layer thickness

Enhanced field bipolar resistive RAM integrated with FDSOI technology

AC coupling modules for bias ladders

Bulk substrates with a self-aligned buried polycrystalline layer

Method and apparatus for using back gate biasing for power amplifiers for millimeter wave devices

Bent polysilicon gate structure for small footprint radio frequency (RF) switch

SOI-based floating gate memory cell

Semiconductor device

Stacked vertical NFET and PFET

Three-dimensional monolithic vertical field effect transistor logic gates

Semiconductor device and manufacturing method thereof

Devices and methods for fully depleted silicon-on-insulator back biasing

Post gate silicon germanium channel condensation and method for producing the same

Method for reducing switch on state resistance of switched-capacitor charge pump using self-generated switching back-gate bias voltage

Fully depleted silicon on insulator integration

Method to fabricate both FD-SOI and PD-SOI devices within a single integrated circuit

Back biasing in SOI FET technology

Method of forming high performance vertical natural capacitor (VNCAP)

Heat dissipation and series resistance reduction of PA and RF switch in SLT by backside thick metal

Hybrid MOS-PCM CMOS SOI switch

DC-coupled high-voltage level shifter

Memory cells and devices

Connection arrangements for integrated lateral diffusion field effect transistors

Current mirror devices using cascode with back-gate bias

Biasing the substrate region of an MOS transistor

Tapered polysilicon gate layout for power handling improvement for radio frequency (RF) switch applications

Junction formation with reduced Cfor 22nm FDSOI devices

Etch stop liner for contact punch through mitigation in SOI substrate

Diffusion break forming after source/drain forming and related IC structure

SRAM bitcell structures facilitating biasing of pull-up transistors

Fully depleted silicon-on-insulator (FDSOI) transistor device and self-aligned active area in FDSOI bulk exposed regions

Device structures with multiple nitrided layers

Systems, methods and apparatus for enabling high voltage circuits

Digital frequency multiplier to generate a local oscillator signal in FDSOI technology

Contact punch through mitigation in SOI substrate

Semiconductor structure including a first transistor at a semiconductor-on-insulator region and a second transistor at a bulk region and method for the formation thereof

Coaxial connector feed-through for multi-level interconnected semiconductor wafers

High density nanosheet diodes

One time programmable read-only memory (ROM) in SOI CMOS

Body tie optimization for stacked transistor amplifier

Conductive contacts in semiconductor on insulator substrate

Methods of forming a device having semiconductor devices on two sides of a buried dielectric layer

Integrated circuits with peltier cooling provided by back-end wiring

Utilization of backside silicidation to form dual side contacted capacitor

Lateral bipolar junction transistor with multiple base lengths

Electronic chip comprising transistors with front and back gates

Germanium lateral bipolar transistor with silicon passivation

On-chip DC-DC power converters with fully integrated GaN power switches, silicon CMOS transistors and magnetic inductors

Apparatus and method of fabrication for GaN/Si transistors isolation

Defect reduction in channel silicon germanium on patterned silicon

Methods, apparatus and system for providing NMOS-only memory cells

Integrated circuit including a dummy gate structure and method for the formation thereof

Grounded die seal integrated circuit structure for RF circuits

Pass-through contact using silicide

Semiconductor structure including a trench capping layer and method for the formation thereof

Reduced parasitic capacitance and contact resistance in extremely thin silicon-on-insulator (ETSOI) devices due to wrap-around structure of source/drain regions

Chip structures with distributed wiring

Self-aligned contacts for vertical field effect transistors

SOI lateral bipolar for integrated-injection logic SRAM

Magnetic-field and magnetic-field gradient sensors based on lateral SOI bipolar transistors

Method of fabrication of ETSOI CMOS device by sidewall image transfer (SIT)

Stacked nanowire semiconductor device

Connecting to back-plate contacts or diode junctions through a RMG electrode and resulting devices

Method and structure for forming dually strained silicon

Method of fabricating ultra-thin inorganic semiconductor film and method of fabricating three-dimensional semiconductor device using the same

Semiconductor device

Method for creating metal gate resistor in FDSOL and resulting device

Stacked nanowire device width adjustment by gas cluster ion beam (GCIB)

Self-aligned contacts for vertical field effect transistors

Compact FDSOI device with Bulex contact extending through buried insulating layer adjacent gate structure for back-bias

VTFT with a top-gate structure

Vertical and planar TFTS on common substrate

Preventing unauthorized use of integrated circuits for radiation-hard applications

Efficient buried oxide layer interconnect scheme

Complementary metal-oxide silicon having silicon and silicon germanium channels

Multiple Vin III-V FETs

Transistor device structure

Modeling charge distribution on FinFET sidewalls

Integrated circuit including a liner silicide with low contact resistance

Schottky clamped radio frequency switch

Method for fabricating semiconductor layers including transistor channels having different strain states, and related semiconductor layers

Integrated circuit and method of forming integrated circuit

Monolithic integration of GaN and InP components