Backside contact to a final substrate

Ion sensor based on differential measurement, and production method

Semiconductor switch

Structure and method to prevent EPI short between trenches in FinFET eDRAM

Structure and method for adjusting threshold voltage of the array of transistors

Suppression of back-gate transistors in RF CMOS switches built on an SOI substrate

FDSOI voltage reference

Systems and methods for a semiconductor structure having multiple semiconductor-device layers

Tunable capacitor for FDSOI applications

METHOD AND APPARATUS FOR HIGH PERFORMANCE PASSIVE-ACTIVE CIRCUIT INTEGRATION

Isolated semiconductor layer over buried isolation layer

Dual channel memory

SEMICONDUCTOR SUBSTRATE AND FABRICATION METHOD THEREOF, AND SEMICONDUCTOR APPARATUS USING THE SAME AND FABRICATION METHOD THEREOF

Dynamic threshold MOS and methods of forming the same

Semiconductor device and method for controlling semiconductor device

Fully-depleted silicon-on-insulator transistors

Method for manufacturing a high-resistivity semiconductor-on-insulator substrate including an RF circuit overlapping a doped region in the substrate

Passive device and radio frequency module formed on high resistivity substrate

Semiconductor device and radio frequency module formed on high resistivity substrate

LOW-WARPAGE SEMICONDUCTOR SUBSTRATE AND METHOD FOR PREPARING SAME

Backside device contact

High power RF switches using multiple optimized transistors

Vertically integrated memory cell

Semiconductor device having antenna and sensor elements

Techniques for multiple gate workfunctions for a nanowire CMOS technology

Semiconductor-on-insulator with back side heat dissipation

Deep trench sidewall etch stop

Memory device and method for manufacturing the same

Electronic device including moat power metallization in trench

Handle substrate of composite substrate for semiconductor, and composite substrate for semiconductor

Three dimensional monolithic LDMOS transistor

Semiconductor device

Method for local isolation between transistors produced on an SOI substrate, in particular an FDSOI substrate, and corresponding integrated circuit

Controllable gated sensor

Embedded carbon-doped germanium as stressor for germanium nFET devices

Semiconductor device and structure

Optical biosensor device

Radio frequency isolation using substrate opening

Radio frequency isolation cavity formation using sacrificial material

Channel SiGe devices with multiple threshold voltages on hybrid oriented substrates, and methods of manufacturing same

SILICON-ON-INSULATOR DEVICES HAVING CONTACT LAYER

Short circuit reduction in a ferroelectric memory cell comprising a stack of layers arranged on a flexible substrate

Cavity formation in semiconductor devices

Backside cavity formation in semiconductor devices

Cavity formation in interface layer in semiconductor devices

Method and structure for forming a dense array of single crystalline semiconductor nanocrystals

Non-volatile composite nanoscopic fabric NAND memory arrays and methods of making same

Integrated scintillator grid with photodiodes

Compact self-aligned implantation transistor edge resistor for SRAM SEU mitigation

Memory structure having array-under-periphery structure

Semiconductor device with buried cavities and dielectric support structures

SUBSTRATE BIAS FOR FIELD-EFFECT TRANSISTOR DEVICES

Semiconductor structure having logic region and analog region

Floating body memory cell having gates favoring different conductivity type regions

Memory device, and semiconductor device and electronic appliance including the same

Body bias multiplexer for stress-free transmission of positive and negative supplies

Electronic device for ESD protection

Preventing unauthorized use of integrated circuits for radiation-hard applications

Programmable structured arrays

Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer

Semiconductor structure with integrated passive structures

High-frequency device including high-frequency switching circuit

Semiconductor structure with integrated passive structures

Methodology to avoid gate stress for low voltage devices in FDSOI technology

Semiconductor-on-insulator (SOI) lateral heterojunction bipolar transistor having an epitaxially grown base

Semiconductor-on-insulator (SOI) lateral heterojunction bipolar transistor having an epitaxially grown base

Apparatus and methods for MOS capacitor structures for variable capacitor arrays

MOS capacitors structures for variable capacitor arrays and methods of forming the same

MOS capacitors flow type devices and methods of forming the same

Semiconductor device structure useful for bulk transistor and method of manufacturing same where a substrate extends commonly over a transistor, an element region, and a separation region

Semiconductor integrated circuit

Programmable active cooling device

Method for making strained semiconductor device and related methods

SILICON-ON-INSULATOR (SOI) WAFERS EMPLOYING MOLDED SUBSTRATES TO IMPROVE INSULATION AND REDUCE CURRENT LEAKAGE

Techniques for multiple gate workfunctions for a nanowire CMOS technology

METHOD OF FORMATION OF A SUBSTRATE OF THE SOI, IN PARTICULAR THE FDSOI, TYPE ADAPTED TO TRANSISTORS HAVING GATE DIELECTRICS OF DIFFERENT THICKNESSES, CORRESPONDING SUBSTRATE AND INTEGRATED CIRCUIT

Efficient buried oxide layer interconnect scheme

Nanowire or 2D material strips interconnects in an integrated circuit cell

Integrated Circuit Assembly and Method of Making

Techniques for dual dielectric thickness for a nanowire CMOS technology using oxygen growth

Method and system for photonic interposer

Method and structure of making enhanced UTBB FDSOI devices

Method and structure of making enhanced UTBB FDSOI devices

Semiconductor device

Electrostatic discharge protection device structures and methods of manufacture

Integrated circuits using silicon on insulator substrates and methods of manufacturing the same

Method of making a CMOS semiconductor device using a stressed silicon-on-insulator (SOI) wafer

Method for fabricating semiconductor structures including fin structures with different strain states, and related semiconductor structures

Manufacturing method for vertical channel gate-all-around MOSFET by epitaxy processes

Memory cell structure, method of manufacturing a memory, and memory apparatus

Semiconductor device with low band-to-band tunneling

Semiconductor structures including rails of dielectric material

Surface devices within a vertical power device

Methods of making integrated circuit assembly with faraday cage and including a conductive ring

Semiconductor device with voids within silicon-on-insulator (SOI) structure and method of forming the semiconductor device

Semiconductor device

Deep trench isolation for RF devices on SOI

Method and system for hybrid integration of optical communication systems

Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer

Vertical transistor and local interconnect structure

Group III-N transistors on nanoscale template structures

Electrostatic discharge (ESD) protection device

Static electricity protection circuit, electro-optical apparatus, and electronic equipment

Semiconductor device

Integrated circuit having a MOM capacitor and method of making same

Floating body storage device employing a charge storage trench

Methods of forming nanotube films and articles

Nonvolatile latch circuit and logic circuit, and semiconductor device using the same

Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxial semiconductor material formed using lateral overgrowth

SEMICONDUCTOR STRUCTURE HAVING FINFET ULTRA THIN BODY

Semiconductor device

III-V CMOS integration on silicon substrate via embedded germanium-containing layer

Metal layout for radio-frequency switches

Driver circuit, signal processing unit having the driver circuit, method for manufacturing the signal processing unit, and display device

Bipolar transistor, band-gap reference circuit and virtual ground reference circuit and methods of fabricating thereof

Isolated semiconductor layer in bulk wafer by localized silicon epitaxial seed formation

Complementary metal-oxide silicon having silicon and silicon germanium channels

Convex shaped thin-film transistor device having elongated channel over insulating layer in a groove of a semiconductor substrate

Superlattice materials and applications

SEMICONDUCTOR DEVICE

Integrated circuit comprising PMOS transistors with different voltage thresholds

Semiconductor device

Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals

Methods and apparatuses for use in tuning reactance in a circuit device

Complementary high mobility nanowire neuron device

Method and structure of making enhanced UTBB FDSOI devices

Stressed nanowire stack for field effect transistor

Stressed nanowire stack for field effect transistor

Semiconductor device having SOI substrate

Nanofluid sensor with real-time spatial sensing

Semiconductor device and method of manufacturing the same

Integrated scintillator grid with photodiodes

Multiple Vin III-V FETs

Multi-orientation SOI substrates for co-integration of different conductivity type semiconductor devices

CMOS transistors including gate spacers of the same thickness

Semiconductor device with mode designation and substrate bias circuits

Semiconductor device and method for manufacturing the same

Semiconductor device including embedded crystalline back-gate bias planes, related design structure and method of fabrication

Deep trench spacing isolation for complementary metal-oxide-semiconductor (CMOS) image sensors

Vertical fin eDRAM

RADIO FREQUENCY DEVICE PROTECTED AGAINST OVERVOLTAGES

Apparatus and methods for variable capacitor arrays

Non-linearity compensation in radio frequency switches and devices

Controllable single pixel sensors

Method to match SOI transistors using a local heater element

DEVICE CONNECTION THROUGH A BURIED OXIDE LAYER IN A SILICON ON INSULATOR WAFER

Radio-frequency devices with gate node voltage compensation

FinFETs having dielectric punch-through stoppers

Uniaxially-strained FD-SOI finFET

Radio-frequency switches having silicon-on-insulator field-effect transistors with reduced linear region resistance

Metal trench capacitor and improved isolation and methods of manufacture

FinFET vertical flash memory

High dose implantation for ultrathin semiconductor-on-insulator substrates

Method to form strained channel in thin box SOI structures by elastic strain relaxation of the substrate

Manufacturing method of semiconductor device with silicon layer containing carbon

Image sensor with vertical electrodes

Front-side imager having a reduced dark current on SOI substrate

Semiconductor device

Semiconductor structure with active device and damaged region

Process for integrated circuit fabrication including a liner silicide with low contact resistance

Dual gate FD-SOI transistor

Semiconductor film with adhesion layer and method for forming the same

Semiconductor system and device

Bipolar transistor manufacturing method

Semiconductor devices with sidewall spacers of equal thickness

Back-illuminated integrated imaging device with simplified interconnect routing

3D high resolution X-ray sensor with integrated scintillator grid

Semiconductor device with anti-fuse memory element

Mechanisms for forming radio frequency (RF) area of integrated circuit structure

Semiconductor-on-insulator (SOI) device and related methods for making same using non-oxidizing thermal treatment

High voltage metal oxide semiconductor field effect transistor integrated into extremely thin semiconductor on insulator process

Method of localized annealing of semi-conducting elements using a reflective area

Semiconductor device having a field effect transistor formed on a silicon-on-insulator substrate and manufacturing method thereof

Semiconductor device and method of manufacturing the same

Solar-powered energy-autonomous silicon-on-insulator device

Schottky clamped radio frequency switch

METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURES INCLUDING TRANSISTOR CHANNELS HAVING DIFFERENT STRAIN STATES, AND RELATED SEMICONDUCTOR STRUCTURES

CMOS nanowire structure

Local interconnect layer enhanced ESD in a bipolar-CMOS-DMOS

Method for fabricating semiconductor layers including transistor channels having different strain states, and related semiconductor layers

Inductor heat dissipation in an integrated circuit

Fully-depleted silicon-on-insulator transistors

Nonvolatile memory device

Dense arrays and charge storage devices

Fabricating method for high voltage semiconductor power switching device

Fully-depleted silicon-on-insulator transistors

Method of fabricating SOI wafer by ion implantation

Device with SRAM memory cells including means for polarizing wells of memory cell transistors

Biosensor devices, systems and methods therefor

Structure and method for reducing substrate parasitics in semiconductor on insulator technology

Semiconductor device, method for manufacturing same, and nonvolatile semiconductor memory device

Method of forming a semiconductor substrate with buried cavities and dielectric support structures

Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction

Boron rich nitride cap for total ionizing dose mitigation in SOI devices

Semiconductor integrated circuit device comprising MISFETs in SOI and bulk subtrate regions

High freuency semiconductor switch and wireless device

Semiconductor device and fabrication method therefor

Method of manufacturing a MISFET on an SOI substrate

Backside source-drain contact for integrated circuit transistor devices and method of making same

Heterogeneous semiconductor material integration techniques

Circuit structures, memory circuitry, and methods

Semiconductor device with surrounding gate transistors in a NOR circuit

Dual channel memory

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Semiconductor device

JUNCTIONLESS NANOWIRE TRANSISTORS FOR 3D MONOLITHIC INTEGRATION OF CMOS INVERTERS

CMOS in situ doped flow with independently tunable spacer thickness

Trap rich layer for semiconductor devices

FIELD EFFECT TRANSISTOR (FET) WITH SELF-ALIGNED CONTACTS, INTEGRATED CIRCUIT (IC) CHIP AND METHOD OF MANUFACTURE

Semiconductor devices and structures

Handler wafer removal by use of sacrificial inert layer

Fabrication of perfectly symmetric gate-all-around FET on suspended nanowire using interface interaction

Semiconductor memory device

Semiconductor device with coils in different wiring layers

Device and method for improving RF performance

Compound for forming organic film, and organic film composition using the same, process for forming organic film, and patterning process

Recess technique to embed flash memory in SOI technology

Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs

Techniques for creating a local interconnect using a SOI wafer

Compound for forming organic film, and organic film composition using the same, process for forming organic film, and patterning process

Dynamic threshold MOS and methods of forming the same

Turnable breakdown voltage RF FET devices

Semiconductor device and method of manufacturing the same

Undercut insulating regions for silicon-on-insulator device

Tunable breakdown voltage RF FET devices

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME

Low leakage dual STI integrated circuit including FDSOI transistors

Dual STI integrated circuit including FDSOI transistors and method for manufacturing the same

Semiconductor structure with integrated passive structures

ESD protection device and related fabrication methods

Method for manufacturing semiconductor device

Lateral MOSFET with dielectric isolation trench

Semiconductor device and method of manufacturing the same

Semiconductor device with six transistors forming a NAND circuit

Memory device and manufacturing method the same

Radio-frequency switch having dynamic body coupling

Field-effect transistor including oxide semiconductor, and memory and semiconductor circuit including the same

Method of forming different voltage devices with high-k metal gate

Integration of optical components in integrated circuits by separating two substrates with an insulation layer

Three dimensional semiconductor device having lateral channel

Transistor and semiconductor device

SOI WITH GOLD-DOPED HANDLE WAFER

Buried signal transmission line

Semiconductor memory having both volatile and non-volatile functionality and method of operating

Radio frequency devices having reduced intermodulation distortion

Single-chip field effect transistor (FET) switch with silicon germanium (SiGe) power amplifier and methods of forming

Semiconductor device including SIU butted junction to reduce short-channel penalty

Semiconductor device and manufacturing method of the same

Method of manufacturing semiconductor device

Backside source-drain contact for integrated circuit transistor devices and method of making same

Tunable breakdown voltage RF FET devices

Flexible active matrix circuits for interfacing with biological tissue

P-FET with strained silicon-germanium channel

Back gate in select transistor for eDRAM

Embedding semiconductor devices in silicon-on-insulator wafers connected using through silicon vias

Method for making strained semiconductor device and related methods

Three-dimensional semiconductor architecture

Semiconductor device with a NAND circuit having four transistors

Semiconductor with a two-input NOR circuit

Semiconductor switch, wireless apparatus, and method of designing semiconductor switch

High density single-transistor antifuse memory cell

Vertically integrated memory cell

3D semiconductor device having two layers of transistors

Semiconductor device with voids within silicon-on-insulator (SOI) structure and method of forming the semiconductor device

Cell string and reading method for the cell string

Memory device, and semiconductor device and electronic appliance including the same

Integrated semiconductor devices with single crystalline beam, methods of manufacture and design structure

Silicon on nothing devices and methods of formation thereof

CMOS photonic inverter

Electrochemical capacitor and semiconductor chip having an electrochemical capacitor

Method of integrating all active and passive optical devices on silicon-based integrated circuit

INTEGRATED CIRCUIT (IC) CHIP HAVING BOTH METAL AND SILICON GATE FIELD EFFECT TRANSISTORs (FETs) AND METHOD OF MANUFACTURE

High-frequency device including high-frequency switching circuit

Silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) standard library cell circuits having a gate back-bias rail(s), and related systems and methods

Semiconductor device and manufacturing method thereof

Field effect transistors including contoured channels and planar channels

Semiconductor device and method of fabricating the same

Memristive RF switches

Silicon and silicon germanium nanowire structures

Semiconductor device and fabricating the same

Semiconductor device and manufacturing method of semiconductor device

Semiconductor device and method for manufacturing the same

High voltage metal oxide semiconductor field effect transistor integrated into extremely thin semiconductor on insulator process

Isolated semiconductor layer over buried isolation layer

Silicon-on-insulator integrated circuit devices with body contact structures

Trap rich layer formation techniques for semiconductor devices

Strain engineering in back end of the line

Integrated circuit comprising transistors with different threshold voltages

Hybrid III-V technology to support multiple supply voltages and off state currents on same chip

Transistor device structure that includes polycrystalline semiconductor thin film that has large grain size

STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM

Semiconductor device including write access transistor having channel region including oxide semiconductor

Semiconductor manufacturing method and semiconductor device

Method and system for monolithic integration of photonics and electronics in CMOS processes

Thin channel-on-insulator MOSFET device with n+ epitaxy substrate and embedded stressor

p-FET with strained silicon-germanium channel

Stressed nanowire stack for field effect transistor

HV complementary bipolar transistors with lateral collectors on SOI with resurf regions under buried oxide

Semiconductor device with peripheral breakdown protection

Thin channel-on-insulator MOSFET device with n+ epitaxy substrate and embedded stressor