Hybrid CMOS nanowire mesh device and PDSOI device

Hybrid CMOS nanowire mesh device and FINFET device

Method for driving semiconductor device

Method and apparatus improving gate oxide reliability by controlling accumulated charge

Semiconductor device

Device with FD-SOI cell and insulated semiconductor contact region and related methods

Memory device, semiconductor device, and electronic device

Method for fabricating array substrate, array substrate and display device

Method of forming a suspended structure and a transistor co-integrated on a same substrate

Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making

Method of forming substrate contact for semiconductor on insulator (SOI) substrate

Complementary SOI lateral bipolar for SRAM in a CMOS platform

Complementary SOI lateral bipolar for SRAM in a CMOS platform

Method for fabricating a connection region in a semiconductor device

Inducing channel stress in semiconductor-on-insulator devices by base substrate oxidation

Thin film transistor comprising pixel electrode

Integrated circuit with a thin body field effect transistor and capacitor

Semiconductor component and methods for producing a semiconductor component

Integrated circuit with a thin body field effect transistor and capacitor

Semiconductor device

Integrated circuit (IC) structure

Recessed gate field effect transistor

On-chip diode with fully depleted semiconductor devices

Structure and method to form passive devices in ETSOI process flow

Semiconductor device having diffusion barrier to reduce back channel leakage

Method and structure for forming on-chip high quality capacitors with ETSOI transistors

Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor

Deep isolation trench structure and deep trench capacitor on a semiconductor-on-insulator substrate

Self-Aligned Silicide Bottom Plate for EDRAM Applications by Self-Diffusing Metal in CVD/ALD Metal Process

Self-aligned silicide bottom plate for eDRAM applications by self-diffusing metal in CVD/ALD metal process

Layout schemes for cascade MOS transistors

Impedance matching network with improved quality factor and method for matching an impedance

Silicon device on SI:C-OI and SGOI and method of manufacture

Thin film transistor and fabricating method

Silicon on nothing devices and methods of formation thereof

Semiconductor device and driving method thereof

SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER, METHOD FOR PRODUCING SEMICONDUCTOR WAFER, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER, METHOD FOR PRODUCING SEMICONDUCTOR WAFER, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

Methods of containing defects for non-silicon device engineering

Non-volatile memory device employing semiconductor nanoparticles

Lateral epitaxial grown SOI in deep trench structures and methods of manufacture

Semiconductor structure with integrated passive structures

Semiconductor-on-insulator (SOI) deep trench capacitor

Method of fabricating isolated capacitors and structure thereof

Circuit for providing a voltage or a current

Self-contained integrated circuit including adjacent cells of different types

Strained semiconductor device and method of making the same

Recessed single crystalline source and drain for semiconductor-on-insulator devices

SOI device with embedded liner in box layer to limit STI recess

Deep trench capacitor

DRAM with dual level word lines

Electrical isolation structures for ultra-thin semiconductor-on-insulator devices

Semiconductor device including an active region and two layers having different stress characteristics

Dynamic random access memory unit and method for fabricating the same

DISPOSABLE CARBON-BASED TEMPLATE LAYER FOR FORMATION OF BORDERLESS CONTACT STRUCTURES

Methods for forming semiconductor device structures

Techniques for gate workfunction engineering to reduce short channel effects in planar CMOS devices

Floating body field-effect transistors, and methods of forming floating body field-effect transistors

CMOS-compatible gold-free contacts

Semiconductor device and method of manufacturing the same

DISPOSABLE CARBON-BASED TEMPLATE LAYER FOR FORMATION OF BORDERLESS CONTACT STRUCTURES

Techniques for gate workfunction engineering to reduce short channel effects in planar CMOS devices

Solid-state image pick-up device and manufacturing method thereof, image-pickup apparatus, semiconductor device and manufacturing method thereof, and semiconductor substrate

Semiconductor-on-insulator device with asymmetric structure

Embedded silicon germanium N-type filed effect transistor for reduced floating body effect

Method and structure for integrating capacitor-less memory cell with logic

Thin integrated circuit chip-on-board assembly and method of making

Power device integration on a common substrate

Radio frequency isolation for SOI transistors

Embedded silicon germanium N-type field effect transistor for reduced floating body effect

Apparatus relating to a memory cell having a floating body

Trap rich layer with through-silicon-vias in semiconductor devices

Photonic modulator with a semiconductor contact

Techniques for providing a semiconductor memory device

Body contacts for FET in SOI SRAM array

Semiconductor structure having NFET extension last implants

Semiconductor structures and devices

Transistor structures and integrated circuitry comprising an array of transistor structures

Semiconductor-on-insulator (SOI) structure with selectivity placed sub-insulator layer void(s) and method of forming the SOI structure

Integrated circuit including transistor structure on depleted silicon-on-insulator, related method and design structure

DRAM with dual level word lines

Integrated circuit having memory cell array including barriers, and method of manufacturing same

On-SOI integrated circuit comprising a lateral diode for protection against electrostatic discharges

Charge breakdown avoidance for MIM elements in SOI base technology and method

Self-protected metal-oxide-semiconductor field-effect transistor

ON-SOI integrated circuit comprising a thyristor (SCR) for protection against electrostatic discharges

Semiconductor device and manufacturing method thereof

Floating body memory cell having gates favoring different conductivity type regions

MOS transistor on SOI protected against overvoltages

Radio-frequency switch system having improved intermodulation distortion performance

Strained silicon and strained silicon germanium on insulator

Circuits, devices, methods and applications related to silicon-on-insulator based radio-frequency switches

Radio-frequency switch having gate node voltage compensation network

Switch linearization by non-linear compensation of a field-effect transistor

Complementary bipolar inverter

Integrated semiconductor devices with single crystalline beam, methods of manufacture and design structure

Strained silicon and strained silicon germanium on insulator field-effect transistor

Interposers including fluidic microchannels and related structures and methods

Semiconductor structures including fluidic microchannels for cooling and related methods

CMOS DEVICES HAVING STRAIN SOURCE/DRAIN REGIONS AND LOW CONTACT RESISTANCE

Undercut insulating regions for silicon-on-insulator device

Semiconductor device with epitaxial source/drain facetting provided at the gate edge

Trap rich layer formation techniques for semiconductor devices

Semiconductor device, method for manufacturing same, and nonvolatile semiconductor memory device

MEMORY CELL WITH ASYMMETRIC READ PORT TRANSISTORS

Ultrathin body fully depleted silicon-on-insulator integrated circuits and methods for fabricating same

Manufacturing process for zero-capacitor random access memory circuits

Compound for forming organic film, and organic film composition using the same, process for forming organic film, and patterning process

SOI semiconductor device comprising a substrate diode and a film diode formed by using a common well implantation mask

Semiconductor structure and method for manufacturing the same

Strained thin body CMOS device having vertically raised source/drain stressors with single spacer

IMPLEMENTING ISOLATED SILICON REGIONS IN SILICON-ON-INSULATOR (SOI) WAFERS USING BONDED-WAFER TECHNIQUE

Spacer isolation in deep trench

Gated diode structure for eliminating RIE damage from cap removal

DRAM with a nanowire access transistor

Process for fabricating an integrated circuit having trench isolations with different depths

Integrated circuit comprising at least one digital output port having an adjustable impedance, and corresponding adjustment method

Semiconductor device

Semiconductor device with isolated body portion

Mixed orientation semiconductor device and method

Switching circuit

Retrograde substrate for deep trench capacitors

Semiconductor active matrix on buried insulator

Semiconductor device with electrically floating body

Silicon-on-insulator high power amplifiers

Retrograde substrate for deep trench capacitors

Epitaxial semiconductor resistor with semiconductor structures on same substrate

Semiconductor active matrix on buried insulator

Inverted thin channel mosfet with self-aligned expanded source/drain

Buried channel field-effect transistors

Buried-channel field-effect transistors

Inverted thin channel mosfet with self-aligned expanded source/drain

On-chip capacitors in combination with CMOS devices on extremely thin semiconductor on insulator (ETSOI) substrates

Semiconductor substrate with transistors having different threshold voltages

Amplification circuit comprising input signal limiting network

Semiconductor device

Complementary metal-oxide-semiconductor (CMOS) device and method

SEMICONDUCTOR SUBSTRATE WITH TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES

Metal-insulator-metal (MIM) capacitor with deep trench (DT) structure and method in a silicon-on-insulator (SOI)

Formation of multi-height MUGFET

JFET device structures and methods for fabricating the same

CMOS WITH SiGe CHANNEL PFETs AND METHOD OF FABRICATION

CMOS WITH SiGe CHANNEL PFETs AND METHOD OF FABRICATION

Diode-triggered silicon controlled rectifier with an integrated diode

Capacitorless DRAM on bulk silicon

BICMOS DEVICES ON ETSOI

TRANSISTOR HAVING A STRESSED BODY

SOI transistors with improved source/drain structures with enhanced strain

MOS having a sic/sige alloy stack

BIPOLAR TRANSISTOR MANUFACTURING METHOD

Pseudo butted junction structure for back plane connection

SOI substrate with acceptor-doped layer

Isolator circuit and semiconductor device

Structure and method of high-performance extremely thin silicon on insulator complementary metal—oxide—semiconductor transistors with dual stress buried insulators

Semiconductor device and manufacturing method of the same

Robust isolation for thin-box ETSOI MOSFETS

Asymmetric FET formed through use of variable pitch gate for use as logic device and test structure

Solar-powered energy-autonomous silicon-on-insulator device

Element array with a plurality of electromechanical conversion devices

SOI devices for plasma display panel driver chip

Asymmetric FET formed through use of variable pitch gate for use as logic device and test structure

Passive devices for FinFET integrated circuit technologies

Nonvolatile memory device and method of fabricating the same

Semiconductor device and structure

Integrated circuit diode

Lateral MOSFET with dielectric isolation trench

Single poly electrically erasable programmable read only memory (single poly EEPROM) device

Nickelide source/drain structures for CMOS transistors

Embedded DRAM for extremely thin semiconductor-on-insulator

Fin field effect transistor and fabrication method

Embedded DRAM memory cell with additional patterning layer for improved strap formation

Nonvolatile latch circuit and logic circuit, and semiconductor device using the same

Semiconductor device

REPLACEMENT GATE ELECTRODE WITH A TANTALUM ALLOY METAL LAYER

Low external resistance ETSOI transistors

Method of forming substrate contact for semiconductor on insulator (SOI) substrate

REPLACEMENT GATE ELECTRODE WITH A TANTALUM ALLOY METAL LAYER

Manufacturing method for a device with transistors strained by silicidation of source and drain zones

LOW EXTERNAL RESISTANCE ETSOI TRANSISTORS

MOSFET with work function adjusted metal backgate

Semiconductor devices having stressor regions and related fabrication methods

Integrated circuit having raised source drains devices with reduced silicide contact resistance and methods to fabricate same

Junction butting on SOI by raised epitaxial structure and method

Flash memory and method for fabricating the same

SOI bipolar junction transistor with substrate bias voltages

Extremely thin semiconductor-on-insulator (ETSOI) layer

Semiconductor substrate for manufacturing transistors having back-gates thereon

Trench capacitor with spacer-less fabrication process

Method of making a 3D integrated circuit

FIELD-EFFECT TRANSISTOR ON A SELF-ASSEMBLED SEMICONDUCTOR WELL

High frequency switch

High density multi-electrode array

MOS field-effect transistor formed on the SOI substrate

High frequency semiconductor switch

High density memory cells using lateral epitaxy

Selective amorphization for electrical signal isolation and linearity in SOI structures

Semiconductor device and method for manufacturing the same

Integrated circuit including DRAM and SRAM/logic

Integrated circuit with a thin body field effect transistor and capacitor

Thermally stable high-K tetragonal HFOlayer within high aspect ratio deep trenches

Integrated Circuit Having Back Gating, Improved Isolation And Reduced Well Resistance And Method To Fabricate Same

Structure and method for using high-K material as an etch stop layer in dual stress layer process

Controlling threshold voltage in carbon based field effect transistors

REDUCTION OF CONTACT RESISTANCE AND JUNCTION LEAKAGE

Replacement gate structure for transistor with a high-K gate stack

Integrated circuit having raised source drains devices with reduced silicide contact resistance and methods to fabricate same

Electrical isolation structures for ultra-thin semiconductor-on-insulator devices

SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME

Integrated circuit having raised source drains devices with reduced silicide contact resistance and methods to fabricate same

Integrated circuit with a thin body field effect transistor and capacitor

Integrated circuit including DRAM and SRAM/logic

Integrated circuit including DRAM and SRAM/logic

SYSTEMS AND METHODS FOR BACKSIDE THRESHOLD VOLTAGE ADJUSTMENT

Self aligned structures and design structure thereof

CMOS having a SiC/SiGe alloy stack

THIN FILM TRANSISTOR AND FABRICATING METHOD

Structure, method and system for complementary strain fill for integrated circuit chips

Isolation region fabrication for replacement gate processing

REDUCTION OF THICKNESS VARIATIONS OF A THRESHOLD SEMICONDUCTOR ALLOY BY REDUCING PATTERNING NON-UNIFORMITIES PRIOR TO DEPOSITING THE SEMICONDUCTOR ALLOY

Integrated circuits with components on both sides of a selected substrate and methods of fabrication

Integrated Circuits on Ceramic Wafers Using Layer Transfer Technology

Integrated circuit device, system, and method of fabrication

Hybrid CMOS nanowire mesh device and PDSOI device

Hybrid CMOS nanowire mesh device and FINFET device

Silicon on insulator integrated high-current N type combined semiconductor device

Transistor, method for fabricating the transistor, and semiconductor device comprising the transistor

Deep isolation trench structure and deep trench capacitor on a semiconductor-on-insulator substrate

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Integrated circuits formed on strained substrates and including relaxed buffer layers and methods for the manufacture thereof

Method and structure for forming on-chip high quality capacitors with ETSOI transistors

Embedded dynamic random access memory device formed in an extremely thin semiconductor on insulator (ETSOI) substrate

Method and structure for forming ETSOI capacitors, diodes, resistors and back gate contacts

On-chip capacitors in combination with CMOS devices on extremely thin semiconductor on insulator (ETSOI) substrates

Semiconductor device including an isolation film buried in a groove

Method of replacing silicon with metal in integrated circuit chip fabrication

Semiconductor structure and method for forming the semiconductor structure

Integrated circuit assembly and method of making

HIGH DENSITY MULTI-ELECTRODE ARRAY

Structure and method to fabricate a body contact

Noble gas implantation region in top silicon layer of semiconductor-on-insulator substrate

Borderless contact for ultra-thin body devices

Polysilicon/metal contact resistance in deep trench

Method, structure and design structure for customizing history effects of SOI circuits

Radio-frequency switches having silicon-on-insulator field-effect transistors with reduced linear region resistance

Semiconductor-on-insulator with back side body connection

CMOS integrated circuit and amplifying circuit

Semiconductor architecture having field-effect transistors especially suitable for analog applications

Integrated semiconductor devices with single crystalline beam, methods of manufacture and design structure

Silicon-on-insulator high power amplifiers

Method for developing a custom device

Integrated semiconductor devices with amorphous silicon beam, methods of manufacture and design structure

Methods of manufacturing integrated semiconductor devices with single crystalline beam

Semiconductor device and method of manufacturing the same

Semiconductor device

Semiconductor device including an oxide semiconductor layer

Integrated circuit having a MOM capacitor and method of making same

Radiation hardened memory cell and design structures

SRAM cell with individual electrical device threshold control

Recessed single crystalline source and drain for semiconductor-on-insulator devices

CMOS compatible BioFET

Dynamic memory cell provided with a field-effect transistor having zero swing

Post-gate shallow trench isolation structure formation

Reducing performance variation of narrow channel devices

Method for fabrication of a semiconductor device and structure

Shallow trench isolation structure having a nitride plug

High-k dielectric and silicon nitride box region

Carbon implant for workfunction adjustment in replacement gate transistor

MOSFET formed on an SOI wafer with a back gate

Carbon implant for workfunction adjustment in replacement gate transistor

Semiconductor device and method for manufacturing semiconductor device

Transistor having reduced channel length

Integrated circuit using FDSOI technology, with well sharing and means for biasing oppositely doped ground planes present in a same well

Semiconductor device

Electric charge flow circuit for a time measurement

Semiconductor integrated circuit device and manufacturing method for semiconductor integrated circuit device

Restricted stress regions formed in the contact level of a semiconductor device

Silicon-on-insulator chip having multiple crystal orientations

Structure and method to form passive devices in ETSOI process flow

Enhancement of charge carrier mobility in transistors

Enhancement of charge carrier mobility in transistors

METHOD FOR FABRICATING JUNCTIONLESS TRANSISTOR

Junctionless transistor

Gettering method for dielectrically isolated devices

Method for producing semiconductor device and semiconductor device having pillar-shaped semiconductor

SENSOR ELEMENT WITH ENGINEERED SILICIDE

SOI integrated circuit comprising adjacent cells of different types

Self-aligned bottom plate for metal high-K dielectric metal insulator metal (MIM) embedded dynamic random access memory

Manufacturing method of oxide semiconductor device

METHOD FOR RADIATION HARDENING AN INTEGRATED CIRCUIT

Non-volatile latch circuit and logic circuit, and semiconductor device using the same

Insulation wall between transistors on SOI

Semiconductor device with work function adjusting layer having varied thickness in a gate width direction and methods of making same

On-chip radiation dosimeter

Semiconductor device with a common back gate isolation region and method for manufacturing the same

Semiconductor device with back gate isolation regions and method for manufacturing the same

Integrated circuits that include deep trench capacitors and methods for their fabrication

Semiconductor device and method for manufacturing semiconductor device

Isolation region fabrication for replacement gate processing

Raised source/drain field effect transistor

High linearity hybrid transistor device