208218 ⎘
Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor; Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions Isolation within the component, i.e. internal isolation
Sub-classes:SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
#2HETEROJUNCTION BIPOLAR TRANSISTOR WITH BURIED TRAP RICH ISOLATION REGION
#3METHOD FOR FORMING AN UNDOPED REGION UNDER A SOURCE/DRAIN
#4metal-oxide-semiconductor transistor and complementary metal-oxide-semiconductor circuit related
#5SEMICONDUCTOR STRUCTURE WITH DEVICE INCLUDING AT LEAST ONE IN-WELL POROUS REGION
#6Fabrication method for JFET with implant isolation
#7SEMICONDUCTOR DEVICE INCLUDING POROUS SEMICONDUCTOR MATERIAL ADJACENT AN ISOLATION STRUCTURE
#8SEMICONDUCTOR SUBSTRATE, AND MANUFACTURING METHOD AND MANUFACTURING APPARATUS OF SEMICONDUCTOR SUBSTRATE
#9SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
#10Semiconductor device and method for forming the same
#11ENHANCEMENT MODE TRANSISTOR WITH A ROBUST GATE AND METHOD
#12SEMICONDUCTOR DEVICE HAVING A TERMINATION REGION WITH DEEP TRENCH ISOLATION
#13DIFFUSION BREAK STRUCTURE FOR TRANSISTORS
#14SEMICONDUCTOR SUBSTRATE, AND MANUFACTURING METHOD AND MANUFACTURING APPARATUS OF SEMICONDUCTOR SUBSTRATE
#15SEMICONDUCTOR DEVICE
#16Advanced etching technologies for straight, tall and uniform fins across multiple fin pitch structures
#17SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
#18TVS WITH ENHANCED REPETITIVE SURGE PERFORMANCE
#19Semiconductor device
#20Semiconductor device
#21METHOD FOR FORMING SEMICONDUCTOR STRUCTURE
#22Semiconductor devices
#23Enhancement High Electron Mobility Transistor and Manufacturing Method Thereof
#24METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE
#25METAL GATE STRUCTURE CUTTING PROCESS
#26MEMORY DEVICE ISOLATION STRUCTURE AND METHOD
#27Heterojunction bipolar transistor with buried trap rich isolation region
#28Porogen bonded gap filling material in semiconductor manufacturing
#29Nitride-based semiconductor device and method for manufacturing the same
#30Bipolar transistor structure with collector on polycrystalline isolation layer and methods to form same
#31Fabrication method for JFET with implant isolation
#32LATERAL POWER SEMICONDUCTOR DEVICE
#33Nitride-based semiconductor device and method for manufacturing the same
#34Nitride-based semiconductor device and method for manufacturing the same
#35DEVICE WITH DUAL ISOLATION STRUCTURE
#36Stacked structure including two-dimensional material and method of fabricating the stacked structure
#37TRANSISTOR WITH BUFFER STRUCTURE HAVING CARBON DOPED PROFILE
#38Bulk substrates with a self-aligned buried polycrystalline layer
#39GALVANIC HIGH VOLTAGE ISOLATION CAPABILITY ENHANCEMENT ON REINFORCED ISOLATION TECHNOLOGIES
#40INTEGRATED CIRCUIT DEVICE
#41Hybrid diffusion break with EUV gate patterning
#42SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
#43SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
#44Semiconductor device and method of fabricating the same
#45Advanced etching technologies for straight, tall and uniform fins across multiple fin pitch structures
#46Semiconductor device and method for forming the same
#47Method for forming an undoped region under a source/drain
#48Semiconductor device
#49Three-phase inverter power chip and preparation method therefor
#50Integration of p-channel and n-channel E-FET III-V devices without parasitic channels
#51Method for forming a high-voltage metal-oxide-semiconductor transistor device
#52Digital isolator
#53Semiconductor structure with hybrid nanostructures
#54Device comprising a transistor
#55Transistors with recessed silicon cap and method forming same
#56Semiconductor device with a crossing region
#57Devices including control logic structures, and related methods
#58Transistor with buffer structure having carbon doped profile
#59Method for forming a high-voltage metal-oxide-semiconductor transistor device
#60Device comprising a transistor
#61Heterojunction bipolar transistor with buried trap rich isolation region
#62III-nitride semiconductor device with non-active regions to shape 2DEG layer
#63Semiconductor device
#64Semiconductor device with isolation and/or protection structures
#65Method for fabricating semiconductor device
#66Bulk semiconductor structure with a multi-level polycrystalline semiconductor region and method
#67TRANSISTOR STRUCTURES AND ASSOCIATED PROCESSES
#68Die-to-die isolation structures for packaged transistor devices
#69Semiconductor constructions, memory arrays, electronic systems, and methods of forming semiconductor constructions
#70Semiconductor device
#71Field-effect transistors with a polycrystalline body in a shallow trench isolation region
#72Method for forming a semiconductor device having protrusion structures on a substrate and a planarized capping insulating layer on the protrusion structures
#73Semiconductor element and method of manufacturing semiconductor element
#74Trap-rich layer in a high-resistivity semiconductor layer
#75Integrated circuit device and preparation method thereof
#76Semiconductor device comprising resurf isolation structure surrounding an outer periphery of a high side circuit region and isolating the high side circuit region from a low side circuit region
#77Integrated circuit devices and methods of fabricating such devices
#78JFET with implant isolation
#79Advanced etching technologies for straight, tall and uniform fins across multiple fin pitch structures
#80Integrated circuit package for isolation dies
#81Metal gate structure cutting process
#82Semiconductor device and method for manufacturing the same
#83Apparatus for controlling driver current for illumination source
#84Semiconductor device and power amplifier module
#85Semiconductor devices with bent portions
#86Multi-depth regions of high resistivity in a semiconductor substrate
#87Integration of p-channel and n-channel E-FET III-V devices without parasitic channels
#88Semiconductor devices having fin field effect transistor (FinFET) structures and manufacturing and design methods thereof
#89Porogen bonded gap filling material in semiconductor manufacturing
#90Semiconductor device having side-diffused trench plug
#91Semiconductor device and semiconductor integrated circuit
#92Metal gate structure of a CMOS semiconductor device and method of forming the same
#93Semiconductor device and fabricating method thereof
#94Bulk substrates with a self-aligned buried polycrystalline layer
#95Device comprising a transistor
#96Method for forming a device comprising a bipolar transistor
#97Semiconductor device and method of fabricating the same
#98Semiconductor device and manufacturing method thereof
#99Devices including control logic structures, and related methods
#100Semiconductor device
#101Devices and methods for radiation hardening integrated circuits using shallow trench isolation
#102Semiconductor structure with nanostructure and method for manufacturing the same
#103Forming isolated contacts in a stacked vertical transport field effect transistor (VTFET)
#104Method for fabricating a semiconductor device
#105Semiconductor device
#106Semiconductor device including a first fin active region, a second fin active region and a field region
#107Nanosheet transistor with fully isolated source and drain regions and spacer pinch off
#108Three dimensional memory device and method for fabricating the same
#109Nanosheet transistor barrier for electrically isolating the substrate from the source or drain regions
#110Gate electrode layout with expanded portions over active and isolation regions
#111Semiconductor device
#112Field plates on two opposed surfaces of double-base bidirectional bipolar transistor: devices, methods, and systems
#113Non-planar integrated circuit structures having asymmetric source and drain trench contact spacing
#114Semiconductor device
#115Memory structure
#116Advanced etching technologies for straight, tall and uniform fins across multiple fin pitch structures
#117Semiconductor constructions, memory arrays, electronic systems, and methods of forming semiconductor constructions
#118SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
#119Semiconductor device and power amplifier module
#120Standard cell architecture for gate tie-off
#121Standard cell architecture for gate tie-off
#122Integrated circuit device including complementary metal-oxide-semiconductor transistor with field cut regions to increase carrier mobility
#123Transistors with recessed silicon cap and method forming same
#124Vertical bi-directional switches and method for making same
#125Methods of fabricating semiconductor devices with gate-all-around structure
#126Fin field effect transistor
#127Semiconductor device and method of forming the same
#128Semiconductor devices having Fin Field Effect Transistor (FinFET) structures and manufacturing and design methods thereof
#129Semiconductor device and fabricating method thereof
#130Semiconductor device and fabricating method thereof
#131Semiconductor device
#132Devices and methods for radiation hardening integrated circuits using shallow trench isolation
#133Semiconductor device with a stacked structure and a capping insulation layer
#134Fin-like field effect transistor (FinFET) device and method of manufacturing same
#135Reducing off-state leakage current in Si/SiGe dual channel CMOS
#136Semiconductor device with an interconnect structure and method for forming the same
#137Field plates on two opposed surfaces of double-base bidirectional bipolar transistor: devices, methods, and systems
#138Integrated resistor for semiconductor device
#139Method for manufacturing a FinFET device
#140Lateral transient voltage suppressor device
#141Semiconductor structure with insulating substrate and fabricating method thereof
#142Semiconductor device and method of fabricating the same
#143Dishing prevention columns for bipolar junction transistors
#144Dishing prevention columns for bipolar junction transistors
#145Cryogenic semiconductor device having buried channel array transistor
#146Three-dimensional semiconductor memory device including a penetration region passing through a gate electrode
#147High voltage device and manufacturing method thereof
#148Semiconductor devices including field effect transistors and methods of forming the same
#149Semiconductor device and method for fabricating the same
#150Semiconductor device and method of manufacturing the same
#151Devices including control logic structures, electronic systems, and related methods
#152SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
#153Method of manufacturing a semiconductor device having side-diffused trench plug
#154Integrated circuit devices
#155Multi-layer integrated circuits having isolation cells for layer testing and related methods
#156Semiconductor device and power amplifier module
#157Bulk substrates with a self-aligned buried polycrystalline layer
#158Avalanche photodiode
#159Standard cell architecture for gate tie-off
#160Semiconductor devices including control logic structures, electronic systems, and related methods
#161Anti-interference semiconductor device for optical transceiver
#162Semiconductor device and method of fabricating the same
#163SEMICONDUCTOR MEMORY STRUCTURE AND METHOD FOR PREPARING THE SAME
#164Semiconductor device and fabricating method thereof
#165Method for manufacturing a FinFET device
#166Semiconductor device and semiconductor integrated circuit
#167Advanced etching technologies for straight, tall and uniform fins across multiple fin pitch structures
#168ISOLATION DEVICE
#169Semiconductor device
#170Transistor layout for improved harmonic performance
#171Integrated circuit devices and methods of fabricating such devices
#172SEMICONDUCTOR TRANSISTOR DEVICE
#173Dishing prevention columns for bipolar junction transistors
#174Field plates on two opposed surfaces of double-base bidirectional bipolar transistor: devices, methods, and systems
#175Electronic systems and methods of forming semiconductor constructions
#176Integrated resistor for semiconductor device
#177SEMICONDUCTOR DEVICES WITH BENT PORTIONS
#178High-voltage LDMOSFET devices having polysilicon trench-type guard rings
#179High voltage device and manufacturing method thereof
#180Logic gate cell structure
#181Semiconductor device and manufacturing method thereof
#182Semiconductor device and fabrication method thereof
#183Fin field effect transistor and fabrication method thereof
#184Isolation devices with faraday shields
#185Diode, semiconductor device, and MOSFET
#186Method and device for embedding flash memory and logic integration in FinFET technology
#187Method and device for embedding flash memory and logic integration in FinFET technology
#188Semiconductor device including a first fin active region and a second fin active region
#189Method of manufacturing semiconductor device on hybrid substrate
#190Semiconductor devices having Fin Field Effect Transistor (FinFET) structures and manufacturing and design methods thereof
#191Integrated circuit comprising at least an integrated antenna
#192Manufacturing method for a film stack of a semiconductor device
#193Semiconductor device and power amplifier module
#194Cost-free MTP memory structure with reduced terminal voltages
#195Power semiconductor device
#196Porogen bonded gap filling material in semiconductor manufacturing
#197Semiconductor device with an interconnect structure and method for forming the same
#198High voltage junction terminating structure of high voltage integrated circuit
#199Structure with local contact for shorting a gate electrode to a source/drain region
#200Memory arrays
#201Fin-like field effect transistor (FinFET) device and method of manufacturing same
#202Electrostatic discharge protection device
#203Contact structure and extension formation for III-V nFET
#204Mechanisms for growing epitaxy structure of finFET device
#205FinFET LDMOS devices with improved reliability
#206Semiconductor device
#207Apparatus for controlling driver current for illumination source
#208Integrated circuit devices and method of manufacturing the same
#209SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
#210Contact structure and extension formation for III-V nFET
#211NVM device in SOI technology and method of fabricating an according device
#212Bridging local semiconductor interconnects
#213Germanium lateral bipolar transistor with silicon passivation
#214Integrated circuit devices and methods of fabricating such devices
#215Semiconductor devices having Fin field effect transistor (FinFET) structures and manufacturing and design methods thereof
#216FETS and methods of forming FETS
#217Fabrication of vertical doped fins for complementary metal oxide semiconductor field effect transistors
#218Fabrication of vertical doped fins for complementary metal oxide semiconductor field effect transistors
#219SEMICONDUCTOR DEVICE HAVING SIDE-DIFFUSED TRENCH PLUG
#220Semiconductor device and manufacturing method thereof
#221Multi-layer integrated circuits having isolation cells for layer testing and related methods
#222SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
#223ISOLATION STRUCTURES FOR CIRCUITS SHARING A SUBSTRATE
#224SEMICONDUCTOR ELEMENT AND PRODUCTION METHOD FOR SAME
#225SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
#226Metal oxide semiconductor cell device architecture with mixed diffusion break isolation trenches
#227Method for fabricating a semiconductor device having a first fin active pattern and a second fin active pattern
#228Block patterning method enabling merged space in SRAM with heterogeneous mandrel
#229Semiconductor devices and methods of manufacturing the same
#230Semiconductor devices including field effect transistors and methods of forming the same
#231Methods and systems for reducing electrical disturb effects between thyristor memory cells using heterostructured cathodes
#232Vertical thyristor memory with minority carrier lifetime reduction
#233Method of localized modification of the stresses in a substrate of the SOI type, in particular FD SOI type, and corresponding device
#234Nitride semiconductor transistor device
#235Semiconductor device having a multi-layer, metal-containing film
#236Local SOI fins with multiple heights
#237Semiconductor device with local interconnect structure and manufacturing method thereof
#238Semiconductor device and electric power control apparatus
#239Structure to prevent lateral epitaxial growth in semiconductor devices
#240Strain engineering devices using partial depth films in through-substrate vias
#241Integrated circuit comprising at least an integrated antenna
#242Power semiconductor device
#243Forming zig-zag trench structure to prevent aspect ratio trapping defect escape
#244Self-adjusted isolation bias in semiconductor devices
#245Nitride semiconductor device and method of manufacturing the same
#246Diode, semiconductor device, and MOSFET
#247Implementing stress in a bipolar junction transistor
#248Replacement gate FinFET process using a sit process to define source/drain regions, gate spacers and a gate cavity
#249Segmented power transistor
#250Vertical semiconductor power component capable of withstanding high voltage
#251Semiconductor device layout structure
#252Fabrication method of a metal gate structure
#253Amplifier device comprising enhanced thermal transfer and structural features
#254Contact structure and extension formation for III-V nFET
#255Contact structure and extension formation for III-V nFET
#256Semiconductor device including nanowire transistor
#257Semiconductor device with an interconnect structure and method for forming the same
#258Adjacent device isolation
#259Methods of manufacturing semiconductor devices including isolation layers
#260Bridging local semiconductor interconnects
#261Compound finFET device including oxidized III-V fin isolator
#262Method for forming Fin field effect transistor (FinFET) device structure
#263SEMICONDUCTOR DEVICE HAVING AN ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT
#264Wing-type projection between neighboring access transistors in memory devices
#265MEMORY DEVICE
#266Local SOI fins with multiple heights
#267Memory cell structure for improving erase speed
#268FIN CUT FOR TIGHT FIN PITCH BY TWO DIFFERENT SIT HARD MASK MATERIALS ON FIN
#269FETs and methods of forming FETs
#270Integrated circuit comprising at least an integrated antenna
#271Integrated multichannel and single channel device structure and method of making the same
#272Method for fabricating an improved field effect device
#273Semiconductor device having a plurality of fins and method for fabricating the same
#274Advanced etching technologies for straight, tall and uniform fins across multiple fin pitch structures
#275Semiconductor device and method for manufacturing the same
#276Semiconductor devices including field effect transistors
#277ESD protection structure and method of fabrication thereof
#278Semiconductor device having metal layer and method of fabricating same
#279Methods for probing semiconductor fins through four-point probe and determining carrier concentrations
#280Insulated gate bipolar transistor
#281Silicon carbide semiconductor device, method of manufacturing silicon carbide semiconductor device and method of designing silicon carbide semiconductor device
#282Methods of forming memory devices with isolation structures
#283Adjacent device isolation
#284Group III nitride integration with CMOS technology
#285Semiconductor device having a plurality of fins and method for fabricating the same
#286Metal gate and manufacturing method thereof
#287Semiconductor device and method of manufacture therefor
#288Methods of forming transistor structures including forming channel material after formation processes to prevent damage to the channel material
#289Transistor structure with reduced parasitic side wall characteristics
#290INTEGRATED CIRCUITS AND METHODS FOR FABRICATING MEMORY CELLS AND INTEGRATED CIRCUITS
#291Semiconductor device structure and method for forming the same
#292Semiconductor device with an interconnect structure and method for forming the same
#293Zig-zag trench structure to prevent aspect ratio trapping defect escape
#294Transient voltage suppressor and ESD protection device and array thereof
#295Fin-FET device and manufacturing method thereof
#296Semiconductor device
#297High voltage lateral DMOS transistor with optimized source-side blocking capability
#298High voltage lateral DMOS transistor with optimized source-side blocking capability
#299Semiconductor devices with structures for suppression of parasitic bipolar effect in stacked nanosheet FETs and methods of fabricating the same
#300Semiconductor device having a substrate including a first active region and a second active region