N-type carrier enhancement in semiconductors

Methods of forming integrated circuits

Semiconductor device and method of manufacturing the same

Strained silicon structure

High performance strained source-drain structure and method of fabricating the same

Semiconductor devices employing high-K dielectric layers as a gate insulating layer and methods of fabricating the same

Method of NiSiGe epitaxial growth by introducing Al interlayer

Method of manufacturing a transistor device having asymmetric embedded strain elements

Performance enhancement in PMOS and NMOS transistors on the basis of silicon/carbon material

Integrated circuits and fabrication methods thereof

Borderless contact for replacement gate employing selective deposition

Self-powered integrated circuit with multi-junction photovoltaic cell

Methods of manufacturing a semiconductor device

Replacement gate having work function at valence band edge

Method of fabricating gate and method of manufacturing semiconductor device using the same

Structure and method for replacement metal gate field effect transistors

Asymmetric hetero-structure FET and method of manufacture

Method of manufacturing a semiconductor device

Method for fabricating a substrate provided with two active areas with different semiconductor materials

Fin-like field effect transistor (FinFET) device and method of manufacturing same

METHOD OF FABRICATING SEMICONDUCTOR DEVICE

Method of manufacturing source/drain structures

Reacted conductive gate electrodes and methods of making the same

Epitaxial growth of crystalline material

Semiconductor devices including compressive stress patterns and methods of fabricating the same

Strained structure of a p-type field effect transistor

Facet-free semiconductor device

FinFET and method of fabricating the same

Fin-like field effect transistor (FinFET) device and method of manufacturing same

Semiconductor device with epitaxial crystal layer embedded within susbstrate of dummy pattern region

Semiconductor Devices Having Shallow Junctions

FET structures with trench implantation to improve back channel leakage and body resistance

Tunnel field effect transistor

SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME

MOS device with varying contact trench lengths

Vertical transistor having first and second tensile layers

SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING THE SAME

Method of forming a semiconductor device and semiconductor device

Semiconductor structure with gate structure, source/drain region and recess filling with epitaxial layer

Non-planar quantum well device having interfacial layer and method of forming same

Stressed barrier plug slot contact structure for transistor performance enhancement

Transistors having stressed channel regions and methods of forming transistors having stressed channel regions

Structure and method for increasing strain in a device

METHODS OF FORMING LOW INTERFACE RESISTANCE CONTACTS AND STRUCTURES FORMED THEREBY

Methods of making random access memory devices, transistors, and memory cells

Metal gate transistor and method for fabricating the same

Lateral power MOSFET device having a liner layer formed along the current path to reduce electric resistance and method for manufacturing the same

Memory devices and memory cells

Transistor devices and methods of making

Multiple-gate transistors with reverse T-shaped fins

Methods of manufacturing semiconductor devices

Strained asymmetric source/drain

Integrated electronic device with edge-termination structure and manufacturing method thereof

Method for fabricating MOS transistor

Vertical-conduction integrated electronic device and method for manufacturing thereof

Integrated electronic device and method for manufacturing thereof

Semiconductor Integrated Circuit Device Including an Epitaxial Layer

Semiconductor structure and method for fabricating the same

FIELD-EFFECT TRANSISTOR

ULTRA-THIN BODY TRANSISTOR AND METHOD FOR MANUFCTURING THE SAME

Method and structure for forming high-K/metal gate extremely thin semiconductor on insulator device

Methods of forming memory cells, memory cells, and semiconductor devices

Field effect transistor device with shaped conduction channel

Transistor component with reduced short-circuit current

Metal semiconductor alloy structure for low contact resistance

Transistor with Embedded Strain-Inducing Material and Dummy Gate Electrodes Positioned Adjacent to the Active Region

Semiconductor device and method for manufacturing the same

Semiconductor device and manufacturing method thereof

Integrated circuit and method of fabrication thereof

Fin-like field effect transistor (FinFET) device and method of manufacturing same

Si-Ge-Si SEMICONDUCTOR STRUCTURE HAVING DOUBLE GRADED JUNCTIONS AND METHOD FOR FORMING THE SAME

Metal-oxide semiconductor transistor

Deposited semiconductor structure to minimize N-type dopant diffusion and method of making

Method for manufacturing semiconductor device with semiconductor materials with different lattice constants

Semiconductor device and method of manufacturing the same

Semiconductor device with side-junction and method for fabricating the same

Asymmetric channel MOSFET

Self-aligned contacts in carbon devices

Process for forming a surrounding gate for a nanowire using a sacrificial patternable dielectric

Methods of manufacturing semiconductor devices with Si and SiGe epitaxial layers

REPLACEMENT GATES TO ENHANCE TRANSISTOR STRAIN

Method to control source/drain stressor profiles for stress engineering

Semiconductor device with gate-undercutting recessed region

Methods for forming semiconductor device structures

Semiconductor device with gate-undercutting recessed region

Delta monolayer dopants epitaxy for embedded source/drain silicide

Methods of manufacturing power semiconductor devices with shield and gate contacts

NOVEL METHOD TO ENHANCE CHANNEL STRESS IN CMOS PROCESSES

Methods of manufacturing power semiconductor devices with trenched shielded split gate transistor

Semiconductor devices fabricated by doped material layer as dopant source

System and method for the manufacture of semiconductor devices by the implantation of carbon clusters

Semiconductor devices having stressor regions and related fabrication methods

Semiconductor device and method of fabricating the same

Fabrication of a vertical heterojunction tunnel-FET

Method to enhance channel stress in CMOS processes

CMOS device with raised source and drain regions

Method of forming metal gate structure and method of forming metal gate transistor

Transistor with embedded strain-inducing material formed in diamond-shaped cavities based on a pre-amorphization

Multi-strained source/drain structures

Modifying work function in PMOS devices by counter-doping

Semiconductor devices including gate structure and method of fabricating the same

Method for fabricating a semiconductor device having an epitaxial channel and transistor having same

Strained channel integrated circuit devices

High-mobility trench MOSFETs

NMOS transistor devices and methods for fabricating same

Semiconductor device having a SiGe feature and a metal gate stack

STRAIN-DIRECT-ON-INSULATOR (SDOI) SUBSTRATE AND METHOD OF FORMING

Semiconductor device having e-fuse structure and method of fabricating the same

Method for fabricating a strained structure

Maintaining Integrity of a High-K Gate Stack After Embedding a Stressor Material by Using a Liner

METHOD FOR FORMING POWER DEVICES WITH CARBON-CONTAINING REGION

CMOS devices having dual high-mobility channels

Semiconductor device and method for manufacturing the same

Monolayer dopant embedded stressor for advanced CMOS

Semiconductor structure for reducing band-to-band tunneling (BTBT) leakage

MOS devices with improved source/drain regions with SiGe

Method for improving device performance using epitaxially grown silicon carbon (SiC) or silicon-germanium (SiGe)

Wide band-gap MOSFETs having a heterojunction under gate trenches thereof and related methods of forming such devices

Method of manufacturing a complementary nanowire tunnel field effect transistor semiconductor device

Method of manufacturing semiconductor device

Method of fabricating gate electrode using a treated hard mask

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor device with buried gates and method for fabricating the same

Method of manufacturing a tunnel transistor and IC comprising the same

Semiconductor device with a buried stressor

Strain preserving ion implantation methods

Methods of forming semiconductor devices having faceted semiconductor patterns

Source/drain strained layers

Method of making a finFET, and finFET formed by the method

Implant damage control by in-situ C doping during sige epitaxy for device applications

CMOS devices with Schottky source and drain regions

MOSFETs with reduced contact resistance

Semiconductor device having field effect transistor and method for fabricating the same

Semiconductor device and method of manufacture thereof

Structure and method for forming planar gate field effect transistor with low resistance channel region

Semiconductor devices with heterojunction barrier regions and methods of fabricating same

Method of fabricating transistor with epitaxial layers having different germanium concentrations

Phosphorus Activated NMOS Using SiC Process

Transistors comprising high-k metal gate electrode structures and adapted channel semiconductor materials

Dual epitaxial process for a finFET device

MOS device with varying trench depth

Semiconductor device and method of manufacturing the same

Methods of manufacturing semiconductor devices including forming (111) facets in silicon capping layers on source/drain regions

Method of manufacturing semiconductor device

Method of fabricating gate electrode using a treated hard mask

Semiconductor device and method of manufacturing semiconductor device

Semiconductor structures and methods of manufacturing the same

Semiconductor device and method of manufacture thereof

Transistor having V-shaped embedded stressor

Planar field effect transistor structure having an angled crystallographic etch-defined source/drain recess and a method of forming the transistor structure

Semiconductor device with group III-V channel and group IV source-drain and method for manufacturing the same

Asymmetric source/drain junctions for low power silicon on insulator devices

Methods for forming NMOS EPI layers

Multilayer hard mask

Method of fabricating multi-fingered semiconductor devices on a common substrate

Transistor device having asymmetric embedded strain elements and related manufacturing method

Transistor having gate dielectric protection and structure

Structure and method of forming buried-channel graphene field effect device

Enhanced integrity of a high-K metal gate electrode structure by using a sacrificial spacer for cap removal

Stress enhanced transistor devices and methods of making

Enhanced confinement of high-K metal gate electrode structures by reducing material erosion of a dielectric cap layer upon forming a strain-inducing semiconductor alloy

High-K metal gate electrode structures formed at different process stages of a semiconductor device

High voltage device with partial silicon germanium epi source/drain

METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATED THEREBY

Forming a non-planar transistor having a quantum well channel

Germanium-based quantum well devices

Metal gate fill and method of making

Tunnel field effect transistors

Method of forming a self-aligned charge balanced power DMOS

Semiconductor device having doped epitaxial region and its methods of fabrication

Two-dimensional condensation for uniaxially strained semiconductor fins

Method of fabricating strained structure in semiconductor device

Non-planar germanium quantum well devices

SEMICONDUCTOR DEVICE HAVING A LOCALLY BURIED INSULATION LAYER AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

Stressed barrier plug slot contact structure for transistor performance enhancement

Vertical PMOS field effect transistor and manufacturing method thereof

NMOS architecture involving epitaxially-grown in-situ N-type-doped embedded eSiGe:C source/drain targeting

Performance enhancement in transistors comprising high-K metal gate stack by reducing a width of offset spacers

Performance enhancement in PFET transistors comprising high-k metal gate stack by increasing dopant confinement

Performance enhancement in transistors comprising high-k metal gate stack by an early extension implantation

REDUCING THE SERIES RESISTANCE IN SOPHISTICATED TRANSISTORS BY EMBEDDING METAL SILICIDE CONTACT REGIONS RELIABLY INTO HIGHLY DOPED SEMICONDUCTOR MATERIAL

Manufacturing method for semiconductor device and semiconductor device

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Technique for enhancing dopant profile and channel conductivity by millisecond anneal processes

Semiconductor device and manufacturing method thereof

Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains

Inducement of strain in a semiconductor layer

Heterojunction device comprising a semiconductor and a resistivity-switching oxide or nitride

Method of forming asymmetric spacers and methods of fabricating semiconductor device using asymmetric spacers

Method of forming strained structures with compound profiles in semiconductor devices

SUBSTANTIALLY LATTICE MATCHED SEMICONDUCTOR MATERIALS AND ASSOCIATED METHODS

Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain

Selective silicon etch process

METHOD OF FABRICATING SEMICONDUCTOR DEVICE

Method of forming epi film in substrate trench

Method for improving transistor performance through reducing the salicide interface resistance

Semiconductor devices having tensile and/or compressive strain and methods of manufacturing and design structure

MOS devices with partial stressor channel

Bi-layer nFET embedded stressor element and integration to enhance drive current

Strained structure of semiconductor device

Controlling the shape of source/drain regions in FinFETs

III-V semiconductor device structures

Integrated circuit structures containing a strain-compensated compound semiconductor layer and methods and systems related thereto

Substrate symmetrical silicide source/drain surrounding gate transistor

High-performance FETs with embedded stressors

3D polysilicon diode with low contact resistance and method for forming same

Method for fabricating transistor with thinned channel

Embedded silicon germanium source drain structure with reduced silicide encroachment and contact resistance and enhanced channel mobility

Semiconductor device structure with strain layer

Structure with isotropic silicon recess profile in nanoscale dimensions

Silicon carbide semiconductor device

Device having self-aligned double gate formed by backside engineering, and device having super-steep retrograded island

Semiconductor device

Application of millisecond heating source for surface treatment

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Buried etch stop layer in trench isolation structures for superior surface planarity in densely packed semiconductor devices

Method for fabricating a MOS transistor with source/well heterojunction and related structure

Accumulation type FinFET, circuits and fabrication method thereof

Germanium silicide layer including vanadium, platinum, and nickel

Bottle-neck recess in a semiconductor device

Semiconductor device and production method thereof

Semiconductor device with field effect transistor and manufacturing method thereof

Extremely thin silicon on insulator (ETSOI) complementary metal oxide semiconductor (CMOS) with in-situ doped source and drain regions formed by a single mask

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Metal oxide semiconductor transistor

Semiconductor device and manufacturing method thereof

Source/drain carbon implant and RTA anneal, pre-SiGe deposition

SOI transistors having an embedded extension region to improve extension resistance and channel strain characteristics

Method for forming high germanium concentration SiGe stressor

Transistors having a composite strain structure, integrated circuits, and fabrication methods thereof

Semiconductor device and manufacturing method of the same

Semiconductor device manufacturing method

Structure and method for forming field effect transistor with low resistance channel region

Semiconductor nanocrystal heterostructures

Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications

FIELD EFFECT TRANSISTOR HAVING CHANNEL SILICON GERMANIUM

Method for improving transistor performance through reducing the salicide interface resistance

Semiconductor wafer, method of manufacturing a semiconductor wafer, and electronic device

METHOD FOR MANUFACTURING SEMICONDUTOR DEVICE WITH STRAINED CHANNEL

Power semiconductor devices having termination structures

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Method of making a hetero tunnel field effect transistor

Insulated Gate Bipolar Transistor (IGBT) Collector Formed with Ge/A1 and Production Method

Phase change memory device and method of manufacturing the same

Semiconductor device having a plurality of phosphorus-doped silicon carbide layers

Semiconductor device having a stress-inducing layer between channel region and source and drain regions

Semiconductor device, method of manufacturing the same, and method of evaluating semiconductor device

Methods for forming a transistor with a strained channel

Strained channel transistor structure and method

Semiconductor device including field effect transistor and method of forming the same

Power amplifier

Semiconductor device and fabrication method thereof

Semiconductor device and manufacturing method thereof

High voltage insulated gate bipolar transistors with minority carrier diverter

Method of manufacturing semiconductor device

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Semiconductor structure having blocks connected by nanowires

Selective epitaxial growth of semiconductor materials with reduced defects

Source/drain strained layers

Modifying work function in PMOS devices by counter-doping

Devices with graphene layers

Formation Of Raised Source/Drain On A Strained Thin Film Implanted With Cold And/Or Molecular Carbon

Inorganic Nanocrystal Bulk Heterojunctions

NMOS transistor devices and methods for fabricating same

MOSFET including epitaxial halo region

N-type carrier enhancement in semiconductors

Integrated circuit system with a floating dielectric region and method of manufacture thereof

Semiconductor device and method of fabricating the same

Source/drain engineering of devices with high-mobility channels

CMOS SiGe channel pFET and Si channel nFET devices with minimal STI recess

Semiconductor device including MISFET

Method of fabricating spacers in a strained semiconductor device

BANDGAP ENGINEERED MOS-GATED POWER TRANSISTORS

Dual-SiGe epitaxy for MOS devices

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Method of fabricating metal oxide semiconductor transistor

CMOS transistors with silicon germanium channel and dual embedded stressors

Chromium doped diamond-like carbon

Silicon carbide semiconductor device and method for manufacturing the same

Twin-drain spatial wavefunction switched field-effect transistors

Adjusting of a non-silicon fraction in a semiconductor alloy during transistor fabrication by an intermediate oxidation process

Asymmetric source/drain junctions for low power silicon on insulator devices

Processing Method and Recording Medium

Method for removing hard masks on gates in semiconductor manufacturing process

Non-volatile semiconductor storage device and method for manufacturing the same

Lattice-mismatched semiconductor structures and related methods for device fabrication

Semiconductor device and manufacturing method of the same

Semiconductor device and method of fabricating the same

Methods of fabricating integrated circuit devices including strained channel regions and related devices

Semiconductor devices

EMBEDDED STRESS ELEMENTS ON SURFACE THIN DIRECT SILICON BOND SUBSTRATES

Semiconductor Devices and Methods of Manufacturing Thereof

Stress optimization in dual embedded epitaxially grown semiconductor processing

Method of manufacturing semiconductor device having stress creating layer

In situ formed drain and source regions including a strain-inducing alloy and a graded dopant profile

Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains

Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain

Transistor devices and methods of making

Semiconductor device and manufacturing method thereof