Method of forming a field effect transistor

Semiconductor device and method for fabricating the same

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCER DEVICE

Method for manufacturing a junction

Adjusting of strain caused in a transistor channel by semiconductor material provided for threshold adjustment

Selective wet etch process for CMOS ICs having embedded strain inducing regions and integrated circuits therefrom

Transistor device comprising an embedded semiconductor alloy having an asymmetric configuration

Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains

Multiple-gate transistors with reverse T-shaped fins

Deposited semiconductor structure to minimize N-type dopant diffusion and method of making

Vertical diode and method for manufacturing same and semiconductor memory device

Substrate Processing Apparatus

Germanium substrate-type materials and approach therefor

High speed lateral heterojunction MISFETs realized by 2-dimensional bandgap engineering and methods thereof

Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions

Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions

Epitaxial wafer and method of manufacturing the same

CMOS transistors with differential oxygen content high-K dielectrics

Structure comprises an As-deposited doped single crystalline Si-containing film

Semiconductor devices and methods of manufacturing thereof

Field effect transistor structure with abrupt source/drain junctions

Semiconductor device and production method thereof

Semiconductor device and method for producing the same

Semiconductor devices having Si and SiGe epitaxial layers

Semiconductor device

Memory cell access device having a pn-junction with polycrystalline and single crystal semiconductor regions

Method for gap filling in a gate last process

Semiconductor structure and method of forming the structure

Fabricating semiconductor structures

Recessed drain and source areas in combination with advanced silicide formation in transistors

Method for making a semiconductor device having metal gate stacks

Methods of forming low interface resistance contacts and structures formed thereby

INTEGRATED CIRCUIT SYSTEM EMPLOYING STRESS-ENGINEERED LAYERS

Method of manufacturing a semiconductor device

Semiconductor transistor having a stressed channel

Low-k isolation spacers for conductive regions

Semiconductor transistor having a stressed channel

Tunnel field effect transistor

Memory devices, transistor devices and related methods

Silicon germanium heterostructure barrier varactor

Method for forming a semiconductor device

Method of manufacturing a transistor and method of manufacturing a semiconductor device

Method of forming source and drain of a field-effect-transistor and structure thereof

Power semiconductor devices and methods of manufacture

CMOS DEVICE COMPRISING NMOS TRANSISTORS AND PMOS TRANSISTORS HAVING INCREASED STRAIN-INDUCING SOURCES AND CLOSELY SPACED METAL SILICIDE REGIONS

RAISE S/D FOR GATE-LAST ILD0 GAP FILLING

Transistor with embedded SI/GE material having enhanced across-substrate uniformity

Power MOSFET having a strained channel in a semiconductor heterostructure on metal substrate

Integrated circuit including a hetero-interface and self adjusted diffusion method for manufacturing the same

Method of fabricating semiconductor device using epitaxial growth inhibiting layers

Transistor having a high-k metal gate stack and a compressively stressed channel

Semiconductor device

FABRICATION AND STRUCTURES OF CRYSTALLINE MATERIAL

Method of defining gate structure height for semiconductor devices

Ultra-shallow junctions using atomic-layer doping

Semiconductor devices and methods of manufacture thereof

Metal gate transistor and method for fabricating the same

Structure and method to form multilayer embedded stressors

Method for mechanical stress enhancement in semiconductor devices

Strained silicon with elastic edge relaxation

Depletion mode trench MOSFET for improved efficiency of DC/DC converter applications

Semiconductor device with a reduced band gap and process

Field effect transistor with suppressed corner leakage through channel material band-edge modulation, design structure and method

Carbon-Doped Epitaxial SiGe

Enhanced dislocation stress transistor

Method for fabricating MOS transistors

IC FORMED WITH DENSIFIED CHEMICAL OXIDE LAYER

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Performance enhancement in PMOS and NMOS transistors on the basis of silicon/carbon material

TRANSISTOR WITH EMBEDDED SI/GE MATERIAL HAVING ENHANCED BORON CONFINEMENT

All around gate type semiconductor device and method of manufacturing the same

MOSFET device with localized stressor

Semiconductor device and method of manufacturing the same

Method of fabricating semiconductor device having a junction extended by a selective epitaxial growth (SEG) layer

Implanted metal silicide for semiconductor device

METAL OXIDE SEMICONDUCTOR DEVICES HAVING IMPLANTED CARBON DIFFUSION RETARDATION LAYERS AND METHODS FOR FABRICATING THE SAME

Transistor device having asymmetric embedded strain elements and related manufacturing method

Semiconductor fabrication process including an SiGe rework method

Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process

CMOS TRANSISTOR AND THE METHOD FOR MANUFACTURING THE SAME

Epitaxial growth of crystalline material

Method for forming double gate and tri-gate transistors on a bulk substrate

Semiconductor nanowire transistor

Semiconductor device with hetero junction

In-situ carbon doped e-SiGeCB stack for MOS transistor

Manufacturing method for semiconductor device and semiconductor device

Method for fabricating super-steep retrograde well MOSFET on SOI or bulk silicon substrate, and device fabricated in accordance with the method

Structure and method for forming power devices with carbon-containing region

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND DEVICE MANUFACTURED BY THE METHOD

Tensile strained NMOS transistor using group III-N source/drain regions

STRESS ENHANCED TRANSISTOR DEVICES AND METHODS OF MAKING

Devices comprising coated semiconductor nanocrystals heterostructures

Integrated circuit having localized embedded SiGe and method of manufacturing

Semiconductor nanowire vertical device architecture

Method of manufacturing a semiconductor device

Methods of manufacturing semiconductor devices and structures thereof

Method for Making Transistors and the Device Thereof

Superjunction trench device formation methods

System and method for the manufacture of semiconductor devices by the implantation of carbon clusters

Reduced floating body effect without impact on performance-enhancing stress

Method of forming stepped recesses for embedded strain elements in a semiconductor device

Semiconductor device and production method thereof

Enhanced stress-retention silicon-on-insulator devices and methods of fabricating enhanced stress retention silicon-on-insulator devices

Source/drain carbon implant and RTA anneal, pre-SiGe deposition

Method for producing nMOS and pMOS devices in CMOS processing

METHOD FOR FORMING CARBON SILICON ALLOY (CSA) AND STRUCTURES THEREOF

Enhanced stress for transistors

Semiconductor device with strained channel and method of fabricating the same

Method of forming a pattern for a semiconductor device and method of forming the related MOS transistor

METHODS FOR MANUFACTURING A HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR USING A HYBRID ORIENTATION TECHNOLOGY WAFER

Methods of fabricating different thickness silicon-germanium layers on semiconductor integrated circuit devices and semiconductor integrated circuit devices fabricated thereby

Complementary field effect transistors having embedded silicon source and drain regions

Scalable power field effect transistor with improved heavy body structure and method of manufacture

MOSFET and production method of semiconductor device

Semiconductor devices having tensile and/or compressive strain and methods of manufacturing and design structure

Semiconductor device and method for fabricating the same

COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR DEVICE WITH EMBEDDED STRESSOR

Self-aligned halo/pocket implantation for reducing leakage and source/drain resistance in MOS devices

Semiconductor device manufacturing method

Epitaxial silicon germanium for reduced contact resistance in field-effect transistors

Field effect structure including carbon alloyed channel region and source/drain region not carbon alloyed

METHOD AND APPARATUS FOR CONTROLLING STRESSED LAYER GATE PROXIMITY

Method to enhance channel stress in CMOS processes

CMOS devices having dual high-mobility channels

Silicon-germanium-carbon semiconductor structure

MOS devices with partial stressor channel

SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE HAVING A LOCALLY BURIED INSULATION LAYER

MOBILITY ENHANCEMENT IN SiGe HETEROJUNCTION BIPOLAR TRANSISTORS

Generating Stress in a Field Effect Transistor

Method for increasing penetration depth of drain and source implantation species for a given gate height

Fabrication of a semiconductor device with stressor

CMOS DEVICE COMPRISING AN NMOS TRANSISTOR WITH RECESSED DRAIN AND SOURCE AREAS AND A PMOS TRANSISTOR HAVING A SILICON/GERMANIUM MATERIAL IN THE DRAIN AND SOURCE AREAS

Method for fabricating a semiconductor device having an epitaxial channel and transistor having same

Method of forming an embedded silicon carbon epitaxial layer

Semiconductor device with strained transistors and its manufacture

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Structure and method for forming field effect transistor with low resistance channel region

Strained channel transistor structure and method

Semiconductor device and method of manufacturing the same

Nonvolatile memory and three-state FETs using cladded quantum dot gate structure

Method and Structure For NFET With Embedded Silicon Carbon

Methods of designing an integrated circuit on corrugated substrate

Recess Etch for Epitaxial SiGe

Strain-direct-on-insulator (SDOI) substrate and method of forming

METHODS FOR FABRICATING SEMICONDUCTOR DEVICES USING THERMAL GRADIENT-INDUCING FILMS

P-channel MOS transistor and fabrication process thereof

Semiconductor device with gate-undercutting recessed region

MOSFET HAVING A HIGH STRESS IN THE CHANNEL REGION

STRAINED-CHANNEL FET COMPRISING TWIST-BONDED SEMICONDUCTOR LAYER

Method for fabricating a semiconductor structures and structures thereof

Hybrid Wafers

INTEGRATION SCHEMES TO AVOID FACETED SIGE

ANNEALING METHOD FOR SIGE PROCESS

Method of manufacturing a semiconductor device

Devices with graphene layers

Field effect transistor structure with an insulating layer at the junction

Method for forming a vertical transistor having tensile layers

SiGe device with SiGe-embedded dummy pattern for alleviating micro-loading effect

Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions

Simple scatterometry structure for Si recess etch control

Protection of SiGe during etch and clean operations

Method of forming a semiconductor device and semiconductor device

Semiconductor device having SiGe semiconductor regions

METHOD AND STRUCTURE FOR SEMICONDUCTOR DEVICES WITH SILICON-GERMANIUM DEPOSITS

Method of reducing embedded SiGe loss in semiconductor device manufacturing

Method of forming a germanium silicide layer, semiconductor device including the germanium silicide layer, and method of manufacturing the semiconductor device

INTEGRATED CIRCUIT SYSTEM EMPLOYING DIFFUSED SOURCE/DRAIN EXTENSIONS

LDMOS with channel stress

Phosphorus Activated NMOS Using SiC Process

MOS Devices Having Elevated Source/Drain Regions

Method of fabricating patterned SOI devices and the resulting device structures

Semiconductor device and method of fabricating the same

Integrated circuit and method of fabrication thereof

Semiconductor component including a short-circuit structure

Semiconductor MOS transistor device and method for making the same

Semiconductor device and fabrication method thereof

Power semiconductor component with charge compensation structure and method for the fabrication thereof

Semiconductor doping with reduced gate edge diode leakage

MOS device with varying trench depth

Method of fabricating semiconductor device

Field effect transistor containing a wide band gap semiconductor material in a drain

Semiconductor superjunction structure

Selective epitaxial growth method using halogen containing gate sidewall mask

Semiconductor device and manufacturing method thereof

High-mobility trench MOSFETs

Method for fabricating super-steep retrograde well MOSFET on SOI or bulk silicon substrate, and device fabricated in accordance with the method

Transistor with a plurality of layers with different Ge concentrations

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Source/drain strained layers

Method of forming conformal silicon layer for recessed source-drain

Planar field effect transistor structure having an angled crystallographic etch-defined source/drain recess and a method of forming the transistor structure

Silicon germanium heterostructure barrier varactor

Methodology of implementing ultra high temperature (UHT) anneal in fabricating devices that contain sige

SEMICONDUCTOR DEVICE INCLUDING MOS FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE

Semiconductor device and method of manufacturing the same

Ultra-abrupt semiconductor junction profile

Semiconductor device and method of manufacturing the same

Semiconductor device and method of producing the same

Method for removing hard masks on gates in semiconductor manufacturing process

Defect-free source/drain extensions for MOSFETS having germanium based channel regions

MOS transistor and CMOS transistor having strained channel epi layer and methods of fabricating the transistors

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

METHOD OF FABRICATING MOS TRANSISTOR AND MOS TRANSISTOR FABRICATED THEREBY

Heterojunction semiconductor device and method

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress

Stressor for engineered strain on channel

FABRICATING METHOD OF SEMICONDUCTOR DEVICE

MOS device with low injection diode

MOS device with integrated schottky diode in active region contact trench

MOS device with Schottky barrier controlling layer

Semiconductor device and method of manufacturing semiconductor device

SEMICONDUCTOR TRANSISTOR HAVING A STRESSED CHANNEL

Method and structure using a pure silicon dioxide hardmask for gate patterning for strained silicon MOS transistors

Germanium substrate-type materials and approach therefor

Replacement gates to enhance transistor strain

Semiconductor device and method of fabricating the same

Self-aligned super stressed PFET

Semiconductor device fabricated by selective epitaxial growth method

Semiconductor device and manufacturing method of the same

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Forming embedded dielectric layers adjacent to sidewalls of shallow trench isolation regions

Semiconductor devices and methods of manufacture thereof

Semiconductor device with semiconductor epitaxial layers buried in source/drain regions, and fabrication method of the same

Metal oxide semiconductor transistor

METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAVING ABRUPT ULTRA SHALLOW EPI-TIP REGIONS

SOI field effect transistor having asymmetric junction leakage

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Semiconductor device and method of manufacture

Deposited semiconductor structure to minimize n-type dopant diffusion and method of making

Source/drain stressors formed using in-situ epitaxial growth

Method for forming a transistor having gate dielectric protection and structure

Methods of making substitutionally carbon-doped crystalline Si-containing materials by chemical vapor deposition

Method of manufacturing complementary metal oxide semiconductor transistors

Methods of fabrication of channel-stressed semiconductor devices

Transistor with differently doped strained current electrode region

Si/SiGe interband tunneling diodes with tensile strain

Silicon-based Ge/SiGe optical interconnects

Field effect transistor structure with abrupt source/drain junctions

Power semiconductor devices with trenched shielded split gate transistor and methods of manufacture

Power semiconductor devices with shield and gate contacts and methods of manufacture

Method of fabricating transistor including buried insulating layer and transistor fabricated using the same

Epitaxial source/drain transistor

Semiconductor device and method for fabricating the same

Structures and methods of forming SiGe and SiGeC buried layer for SOI/SiGe technology

Semiconductor device fabrication method, semiconductor device, and semiconductor layer formation method

P-DOPED REGION WITH IMPROVED ABRUPTNESS

CMOS transistors with differential oxygen content high-k dielectrics

Forming silicides with reduced tailing on silicon germanium and silicon

Channel strain engineering in field-effect-transistor

Semiconductor device with strain in channel region and its manufacture method

Semiconductor devices and methods of manufacturing thereof

Method of manufacturing semiconductor device and semiconductor device manufactured thereof

Methods for forming a transistor

METHOD OF FORMING A SEMICONDUCTOR STRUCTURE COMPRISING AN IMPLANTATION OF IONS IN A MATERIAL LAYER TO BE ETCHED

Method of making a semiconductor device with embedded stressor

Integrated circuit structures with multiple FinFETs

Semiconductor substrates having useful and transfer layers

Semiconductor substrates having useful and transfer layers

Integrated circuit on corrugated substrate

Semiconductor devices having recesses filled with semiconductor materials

FABRICATION OF TRANSISTORS WITH A FULLY SILICIDED GATE ELECTRODE AND CHANNEL STRAIN

Semiconductor device having tipless epitaxial source/drain regions

Methods for forming a transistor

MOS devices having elevated source/drain regions

Recess etch for epitaxial SiGe

ENHANCED HOLE MOBILITY P-TYPE JFET AND FABRICATION METHOD THEREFOR

JUNCTION FIELD EFFECT TRANSISTORS IN GERMANIUM AND SILICON-GERMANIUM ALLOYS AND METHOD FOR MAKING AND USING

Semiconductor device and a method for manufacturing a semiconductor device

MOS devices with improved source/drain regions with SiGe

Semiconductor device and a method for manufacturing a semiconductor device

Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors

Method of forming a cross-section hourglass shaped channel region for charge carrier mobility modification

Stressed MOS device

Polycrystalline SiGe Junctions for advanced devices

Semiconductor substrates having useful and transfer layers

Semiconductor structure including laminated isolation region

Semiconductor device structure with strain layer and method of fabricating the semiconductor device structure

Silicon layer for stopping dislocation propagation

SILICIDE FORMATION FOR eSiGe USING SPACER OVERLAPPING eSiGe AND SILICON CHANNEL INTERFACE AND RELATED PFET

METHOD OF FABRICATING SOI nMOSFET AND THE STRUCTURE THEREOF

Semiconductor device having self-aligned epitaxial source and drain extensions

Carbon-Doped Epitaxial SiGe

METHOD OF MANUFACTURING A MOS TRANSISTOR DEVICE

Methods of forming improved EPI fill on narrow isolation bounded source/drain regions and structures formed thereby

METHODS OF FORMING IMPROVED EPI FILL ON NARROW ISOLATION BOUNDED SOURCE/DRAIN REGIONS AND STRUCTURES FORMED THEREBY

Ultra-abrupt semiconductor junction profile

Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereof

CRYSTALLOGRAPHIC RECESS ETCH FOR EMBEDDED SEMICONDUCTOR REGION

Forming a non-planar transistor having a quantum well channel

Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications

Forming a type I heterostructure in a group IV semiconductor

METHOD OF FORMING SELECTIVE AREA COMPOUND SEMICONDUCTOR EPITAXIAL LAYER

Method of forming asymmetric spacers and methods of fabricating semiconductor device using asymmetric spacers

Surface parallel modulator

Heterojunction bipolar transistor

Semiconductor device and method of manufacturing semiconductor device

Semiconductor device including complementary MOS transistor having a strained Si channel