SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD AND STORAGE MEDIUM

STRESS ENHANCED MOS TRANSISTOR AND METHODS FOR ITS FABRICATION

Method of fabricating semiconductor device

Strained silicon with elastic edge relaxation

Structure and method for forming accumulation-mode field effect transistor with improved current capability

STRAINED SILICON MADE BY PRECIPITATING CARBON FROM Si(1-x-y)GexCy ALLOY

Method for fabricating strained-silicon metal-oxide semiconductor transistors

Forming a semiconductor device having epitaxially grown source and drain regions

MRAM Memory conditioning

Semiconductor device having a strained semiconductor alloy concentration profile

Formation of a selective carbon-doped epitaxial cap layer on selective epitaxial SiGe

Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance

Methods of forming inter-poly dielectric (IPD) layers in power semiconductor devices

Semiconductor component with vertical structures having a high aspect ratio and method

Multi-layer source/drain stressor

Power Semiconductor Devices with Barrier Layer to Reduce Substrate Up-Diffusion and Methods of Manufacture

Semiconductor component comprising a drift zone and a drift control zone

Polysilicon gate formation by in-situ doping

Polysilicon gate formation by in-situ doping

Fabrication of transistors with a fully silicided gate electrode and channel strain

CMOS devices with schottky source and drain regions

Scalable power field effect transistor with improved heavy body structure and method of manufacture

METHODS OF FABRICATING INTEGRATED CIRCUIT DEVICES INCLUDING STRAINED CHANNEL REGIONS AND RELATED DEVICES

Semiconductor structure and method of forming the structure

Semiconductor device and method of fabricating the same

Nanowire heterostructures

GeSiSn-based compounds, templates, and semiconductor structures

Semiconductor structure including doped silicon carbon liner layer and method for fabrication thereof

Strained MOS device and methods for forming the same

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD

Selective epitaxy process control

Method for forming silicon/germanium containing drain/source regions in transistors with reduced silicon/germanium loss

Method of forming a silicide layer while applying a compressive or tensile strain to impurity layers

Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain

N-FETS WITH TENSILELY STRAINED SEMICONDUCTOR CHANNELS, AND METHOD FOR FABRICATING SAME USING BURIED PSEUDOMORPHIC LAYERS

Transistor with embedded silicon/germanium material on a strained semiconductor on insulator substrate

Strained MOS devices using source/drain epitaxy

Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods

ETCHING METHOD AND STRUCTURE IN A SILICON RECESS FOR SUBSEQUENT EPITAXIAL GROWTH FOR STRAINED SILICON MOS TRANSISTORS

Integrated circuit system employing stress-engineered spacers

FABRICATION METHODS FOR MOS DEVICE AND CMOS DEVICE

Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Method of forming source and drain of field-effect-transistor and structure thereof

Method of fabricating a strained silicon channel metal oxide semiconductor transistor

Structure and method for mobility enhanced MOSFETs with unalloyed silicide

Tuned tensile stress low resistivity slot contact structure for n-type transistor performance enhancement

Stressed barrier plug slot contact structure for transistor performance enhancement

STRESS LINER SURROUNDED FACETLESS EMBEDDED STRESSOR MOSFET

Stack SiGe for short channel improvement

Methods of fabricating a semiconductor device using a cyclic selective epitaxial growth technique and semiconductor devices formed using the same

Selective etch for patterning a semiconductor film deposited non-selectively

Trenched shield gate power semiconductor devices and methods of manufacture

Non-volatile semiconductor storage device and method for manufacturing the same

Trench type MOSFET and method of fabricating the same

Structure and method for improved stress and yield in pFETS with embedded SiGe source/drain regions

SEMICONDUCTOR DEVICE WITH IMPROVED SOURCE AND DRAIN AND METHOD OF MANUFACTURING THE SAME

INTEGRATED CIRCUIT SYSTEM EMPLOYING DIFFERENTIAL SPACERS

Semiconductor heterostructure

Bulk non-planar transistor having strained enhanced mobility and methods of fabrication

Semiconductor device, method of manufacturing the same, and method of evaluating semiconductor device

Methods of making power semiconductor devices with thick bottom oxide layer

Power semiconductor devices having termination structures and methods of manufacture

Transistor with improved tip profile and method of manufacture thereof

Method of fabricating CMOS transistor and CMOS transistor fabricated thereby

Germanium semiconductor device and method of manufacturing the same

Inducement of strain in a semiconductor layer

Formation and treatment of epitaxial layer containing silicon and carbon

SEMICONDUCTOR DEVICES WITH BURIED ISOLATION REGIONS

Methods for forming III-V semiconductor device structures

MIS-type semiconductor device

Dual-SiGe epitaxy for MOS devices

Raised STI structure and superdamascene technique for NMOSFET performance enhancement with embedded silicon carbon

Method for forming a strained channel in a semiconductor device

Methods of Forming Field Effect Transistors Having Silicon-Germanium Source and Drain Regions

STRUCTURE AND METHOD TO IMPROVE SHORT CHANNEL EFFECTS IN METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS

SEMICONDUCTOR DEVICE

Active regions with compatible dielectric layers

Semiconductor structure having undercut-gate-oxide gate stack enclosed by protective barrier material

Silicide formation on SiGe

Etching method and structure using a hard mask for strained silicon MOS transistors

Stress enhanced MOS transistor and methods for its fabrication

Method of making a strained semiconductor device

Transistor structure and manufacturing method thereof

CMOS device with raised source and drain regions

Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain

Defect reduction using aspect ratio trapping

MOS devices with continuous contact etch stop layer

Semiconductor MOS transistor device and method for making the same

Method of manufacturing complementary metal oxide semiconductor transistor

SiGe selective growth without a hard mask

Field effect transistor comprising a stressed channel region and method of forming the same

STRUCTURE AND METHOD FOR MANUFACTURING HIGH PERFORMANCE AND LOW LEAKEAGE FIELD EFFECT TRANSISTOR

Formation of strain-inducing films using hydrogenated amorphous silicon

Semiconductor Device Including Nickel Alloy Silicide Layer Having Uniform Thickness and Method of Manufacturing the Same

Semiconductor device including field effect transistor and method of forming the same

MOS devices with partial stressor channel

Semiconductor device including field effect transistor and method of forming the same

Tunnel effect transistors based on silicon nanowires

Method of making a semiconductor structure

MOS transistor with in-channel and laterally positioned stressors

MOS devices with source/drain regions having stressed regions and non-stressed regions

HETROJUNCTION BIPOLAR TRANSISTOR (HBT) WITH PERIODIC MULTILAYER BASE

Heterojunction tunneling field effect transistors, and methods for fabricating the same

Superjunction trench device and method

Strained semiconductor power device and method

Semiconductor superjunction structure

Method for improving transistor performance through reducing the salicide interface resistance

Semiconductor system using germanium condensation

Methods for controlling thickness uniformity of SiGe regions

MOS transistor and fabrication thereof

Low-k isolation spacers for conductive regions

CMOS devices with graded silicide regions

Semiconductor device and manufacturing method thereof

Field effect transistor and method of forming a field effect transistor

Raised STI structure and superdamascene technique for NMOSFET performance enhancement with embedded silicon carbon

Semiconductor device and method of manufacturing the same

Semiconductor device including a germanium silicide film on a selective epitaxial layer

BORON DOPED SiGe HALO FOR NFET TO CONTROL SHORT CHANNEL EFFECT

Body-tied, strained-channel multi-gate device and methods of manufacturing same

Semiconductor device and method of manufacturing the same

Method and apparatus for mobility enhancement in a semiconductor device

Structure and method to form multilayer embedded stressors

METHOD OF REDUCING A ROUGHNESS OF A SEMICONDUCTOR SURFACE

CMOS devices with stressed channel regions, and methods for fabricating the same

Plasma implantated impurities in junction region recesses

Lattice-mismatched semiconductor structures and related methods for device fabrication

Junction leakage reduction in SiGe process by implantation

Junction leakage reduction in SiGe process by tilt implantation

Strained semiconductor device and method of making same

Selective epitaxial formation of semiconductor films

CMOS S/D SiGe DEVICE MADE WITH ALTERNATIVE INTEGRATION PROCESS

Strain-inducing semiconductor regions

Recessed drain extensions in transistor device

Method of fabricating a transistor structure

Semiconductor devices and methods of forming the same

Method of manufacturing metal oxide semiconductor and complementary metal oxide semiconductor

High-voltage field-effect transistor

Silicon carbide semiconductor device

Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors

Modifying work function in PMOS devices by counter-doping

Method of ultra-shallow junction formation using Si film alloyed with carbon

Method of forming a field effect transistor

METHOD FOR MAKING SEMICONDUCTOR TRANSISTOR

Method of manufacturing semiconductor device, and semiconductor device

Crystallographic preferential etch to define a recessed-region for epitaxial growth

Semiconductor devices and method of manufacturing them

Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions

Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereof

Semiconductor device with recessed channel

Structure and fabrication method of a selectively deposited capping layer on an epitaxially grown source drain

Method to control source/drain stressor profiles for stress engineering

Semiconductor device having a heterojunction diode and manufacturing method thereof

Method for forming embedded strained drain/source regions based on a combined spacer and cavity etch process

Epitaxial silicon germanium for reduced contact resistance in field-effect transistors

Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions

Semiconductor device and method of fabricating the same

Heterojunction device comprising a semiconductor and a resistivity-switching oxide or nitride

Technique for providing stress sources in MOS transistors in close proximity to a channel region

Selective etch for patterning a semiconductor film deposited non-selectively

SEMICONDUCTOR DEVICE

Trench type MOSgated device with strained layer on trench sidewall

Strained silicon with elastic edge relaxation

Semiconductor device with stressors and method therefor

Semiconductor devices and methods of manufacturing thereof

Selective epitaxy process with alternating gas supply

Semiconductor process integrating source/drain stressors and interlevel dielectric layer stressors

Semiconductor device fabricated by selective epitaxial growth method

Semiconductor device and method of manufacturing the same

Semiconductor device with strained transistors and its manufacture

Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain

ENHANCED SILICON-ON-INSULATOR (SOI) TRANSISTORS AND METHODS OF MAKING ENHANCED SOI TRANSISTORS

Diffusion layer for stressed semiconductor devices

Resolving pattern-loading issues of SiGe stressor

SEMICONDUCTOR DEVICE INCLUDING MISFET

Field effect transistor with suitable source, drain and channel materials and integrated circuit comprising same

Semiconductor MOS transistor device and method for making the same

Polysilicon gate doping method and structure for strained silicon MOS transistors

Stressed-channel CMOS transistors

Solutions for integrated circuit integration of alternative active area materials

Semiconductor device and its manufacturing method capable of suppressing junction leakage current

Heterojunction tunneling field effect transistors, and methods for fabricating the same

Defect-free SiGe source/drain formation by epitaxy-free process

PFETs and methods of manufacturing the same

Semiconductor device using SiGe for substrate

Abrupt junction formation by atomic layer epitaxy of in situ delta doped dopant diffusion barriers

Tensile strained NMOS transistor using group III-N source/drain regions

Semiconductor nanocrystal heterostructures

Low leakage heterojunction vertical transistors and high performance devices thereof

System and method for the manufacture of semiconductor devices by the implantation of carbon clusters

Multigate device with recessed strain regions

Replacement gates to enhance transistor strain

Semiconductor device and method of manufacturing the same

Strained silicon MOS device with box layer between the source and drain regions

Integrated circuit on corrugated substrate

Embedded stressor structure and process

Semiconductor device and method of manufacturing the same

Semiconductor device having high drive current and method of manufacture therefor

Semiconductor device and semiconductor device manufacturing method

Method for fabricating an NMOS transistor

SIDEWALL MOSFETS WITH EMBEDDED STRAINED SOURCE/DRAIN

Method for fabricating a semiconductor component

Power semiconductor component with charge compensation structure and method for the fabrication thereof

Method of manufacturing a DMOS trench transistor

Integration scheme method and structure for transistors using strained silicon

Single mask scheme method and structure for integrating PMOS and NMOS transistors using strained silicon

Technique for providing multiple stress sources in NMOS and PMOS transistors

Technique for strain engineering in Si-based Transistors by using embedded semiconductor layers including atoms with high covalent radius

Implant damage control by in-situ C doping during SiGe epitaxy for device applications

Embedded strain layer in thin SOI transistors and a method of forming the same

Ultra shallow junction formation by solid phase diffusion

STRUCTURE AND METHOD FOR MANUFACTURING HIGH PERFORMANCE AND LOW LEAKAGE FIELD EFFECT TRANSISTOR

Methods to fabricate MOSFET devices using a selective deposition process

Phosphorus activated NMOS using SiC process

Strained-induced mobility enhancement nano-device structure and integrated process architecture for CMOS technologies

Method of fabricating strained-silicon transistors and strained-silicon CMOS transistors

Phosphorus Activated NMOS Using SiC Process

METHOD TO FORM A DEVICE ON A SOI SUBSTRATE

Method and structure using a pure silicon dioxide hardmask for gate patterning for strained silicon MOS transistors

Method of fabricating MOS transistor having epitaxial region

Multistep etching method

Mobility enhancement in SiGe heterojunction bipolar transistors

Technique for forming recessed strained drain/source regions in NMOS and PMOS transistors

MOS devices with reduced recess on substrate surface

Formation of strained Si channel and SiGesource/drain structures using laser annealing

Method for forming uniaxially strained devices

Methods for fabricating a stressed MOS device

Semiconductor device

Strained channel transistor and method of fabricating the same

CMOS transistor with high drive current and low sheet resistance

Method and structure to prevent silicide strapping of source/drain to body in semiconductor devices with source/drain stressor

Method to engineer etch profiles in Si substrate for advanced semiconductor devices

Methods to selectively protect NMOS regions, PMOS regions, and gate layers during EPI process

Structure and method for improved stress and yield in pFETs with embedded SiGe source/drain regions

Semiconductor device and production method thereof

Polycrystalline SiGe junctions for advanced devices

Transistor with improved tip profile and method of manufacture thereof

Integrated circuit on corrugated substrate

Semiconductor device and method of fabricating the same

Semiconductor device

Structure and method for making strained channel field effect transistor using sacrificial spacer

Strained field effect transistors

Power trench MOSFETs having SiGe/Si channel structure

Methods for forming a transistor and modulating channel stress

Semiconductor device and production method thereof

Method for fabricating transistor with thinned channel

Semiconductor device fabrication method

Semiconductor device and fabrication process thereof

Semiconductor substrate and field-effect transistor, and manufacturing method for same

Semiconductor device having a plurality of different layers and method therefor

Methods of making substitutionally carbon-doped crystalline Si-containing materials by chemical vapor deposition

GeSOI transistor with low junction current and low junction capacitance and method for making the same

Selective deposition of silicon-containing films

Structures and methods for forming a locally strained transistor

SOI bottom pre-doping merged e-SiGe for poly height reduction

Enhanced silicon-on-insulator (SOI) transistors and methods of making enhanced SOI transistors

Step-embedded SiGe structure for PFET mobility enhancement

Method for making a semiconductor device with strain enhancement

Transistor fabrication using double etch/refill process

Methods of forming stress enhanced PMOS structures

Method of fabricating a field effect transistor structure with abrupt source/drain junctions

Strained-channel semiconductor structure and method for fabricating the same

P-channel MOS transistor, semiconductor integrated circuit device and fabrication process thereof

Selective epitaxy process with alternating gas supply

Semiconductor transistor

Power semiconductor devices and methods of manufacture

Power semiconductor devices and methods of manufacture

Methods of depositing electrically active doped crystalline Si-containing films

Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress

P-channel MOS transistor and fabrication process thereof

SEMICONDUCTOR INTEGRATED CIRCUIT AND CMOS TRANSISTOR

Semiconductor device and manufacturing method thereof

Semiconductor device and manufacturing method thereof

Memory devices, transistors, and memory cells

Metal hard mask method and structure for strained silicon MOS transistors

Methods of fabricating contact regions for FET incorporating SiGe

Semiconductor substrates having useful and transfer layers

PMOS transistor with discontinuous CESL and method of fabrication

Semiconductor device with compressive and tensile stresses

Semiconductor substrates having useful and transfer layers

In situ formed halo region in a transistor device

Semiconductor devices with buried isolation regions

Asymmetric spacers and asymmetric source/drain extension layers

Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration

Selective deposition

SiSnGeand related alloy heterostructures based on Si, Ge and Sn

NFET and PFET devices and methods of fabricating same

Insulated gate field-effect transistor

Semiconductor transistor having a stressed channel

MOSFET device with localized stressor

Plasma implantation of impurities in junction region recesses

Semiconductor device and fabrication method thereof

Tailoring channel strain profile by recessed material composition control

Ge-Si quantum well structures

CMOS device with selectively formed and backfilled semiconductor substrate areas to improve device performance

Bandgap engineered MOS-gated power transistors

Method of fabricating transistor including buried insulating layer and transistor fabricated using the same

Selective epitaxy process with alternating gas supply

Integration of silicon carbide into DRAM cell to improve retention characteristics

Trench MOSFET and method of manufacturing same