208282 ⎘
Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor; Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group , e.g. alloys in different semiconductor regions, e.g. heterojunctions
Semiconductor device having tipless epitaxial source/drain regions
#602Differentiated voltage threshold metal gate structures for advanced integrated circuit structure fabrication
#603Isolation structure for stacked vertical transistors
#604Semiconductor structure with patterned fin structure
#605Semiconductor devices and methods of manufacturing the same
#606Structure and method for SRAM FinFET device having an oxide feature
#607Semiconductor structure and fabrication method thereof
#608Multi-layer thyristor random access memory with silicon-germanium bases
#609Method for forming semiconductor device structure with isolation feature
#610Gate voltage-tunable electron system integrated with superconducting resonator for quantum computing device
#611FinFETs with source/drain cladding
#612Electronic device including at least one nano-object
#613Dual metal gate structures for advanced integrated circuit structure fabrication
#614Method and structure for FinFET device
#615Source or drain structures for germanium N-channel devices
#616Structure of semiconductor device structure having fins
#617Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures
#618Hybrid scheme for improved performance for P-type and N-type FinFETs
#619Semiconductor component having a fin and an epitaxial contact structure over an epitaxial layer thereof
#620Methods of forming FinFET devices
#621Manufacturing method of a semiconductor device and a plasma processing apparatus
#622Circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation, and related methods
#623Method for forming fin field effect transistor (FinFET) device structure
#624Method of forming source/drain epitaxial stacks
#625Semiconductor device including a first fin active region, a second fin active region and a field region
#626Semiconductor structure with protection layer
#627Semiconductor device and method
#628Semiconductor device including a Fin-FET and method of manufacturing the same
#629Semiconductor device including a Fin-FET and method of manufacturing the same
#630Fin spacer protected source and drain regions in FinFETs
#631Vertical tunneling FinFET
#632Semiconductor structure and process thereof
#633Sensors based on a heterojunction bipolar transistor construction
#634Self-aligned epitaxy layer
#635Semiconductor device and manufacturing method thereof
#636High surface dopant concentration formation processes and structures formed thereby
#637Nanosheet transistor bottom isolation
#638Method for forming semiconductor device structure
#639Gate to source/drain leakage reduction in nanosheet transistors via inner spacer optimization
#640Semiconductor device and method of manufacturing the same
#641Contact resistance reduction employing germanium overlayer pre-contact metalization
#642Field effect transistor with channel layer with atomic layer, and semiconductor device including the same
#643Semiconductor device, method of manufacturing the same and electronic device including the device
#644Etchstop regions in fins of semiconductor devices
#645Semiconductor device
#646Quantum dot devices
#647SiC epitaxial wafer, semiconductor device, and power converter
#648Semiconductor device having asymmetrical source/drain
#649Contact resistance reduction in nanosheet device structure
#650Nanosheet transistor barrier for electrically isolating the substrate from the source or drain regions
#651FinFET devices and methods of forming
#652Semiconductor device and method
#653Method for forming source/drain contacts
#654Forming shallow trench isolation regions for nanosheet field-effect transistor devices using sacrificial epitaxial layer
#655Method for manufacturing semiconductor device
#656Single process for liner and metal fill
#657Formation method of semiconductor device with low resistance contact
#658Reducing band-to-band tunneling in semiconductor devices
#659Semiconductor structure, static random access memory and fabrication method thereof
#660Structure and formation method of fin-like field effect transistor
#661Semiconductor device having source/drain with a protrusion
#662Gate-all-around field-effect transistor devices having source/drain extension contacts to channel layers for reduced parasitic resistance
#663Field-effect transistors with asymmetric gate stacks
#664Method of removing an etch mask
#665Wrap-around contact on FinFET
#666Semiconductor structure with improved source drain epitaxy
#667Semiconductor device structure with barrier layer and method for forming the same
#668METHOD FOR MANUFACTURING SELF-ALIGNED SIGE HBT DEVICE BY NONSELECTIVE EPITAXY
#669Sidewall image transfer nanosheet
#670Nanosheet one transistor dynamic random access device with silicon/silicon germanium channel and common gate structure
#671Semiconductor device
#672Semiconductor device with source/drain structures
#673Semiconductor device and manufacturing method thereof
#674Semiconductor device having a necked semiconductor body and method of forming semiconductor bodies of varying width
#675Semiconductor devices having a fin-shaped active region and methods of manufacturing the same
#676FinFET CMOS with asymmetric gate threshold voltage
#677Semiconductor apparatus including different thermal resistance values for different heat transfer paths
#678Silicon and silicon germanium nanowire structures
#679Fin patterning for advanced integrated circuit structure fabrication
#680Fin field effect transistor (FinFET) device and method for forming the same
#681Vertical field effect transistor and semiconductor device including the same
#682Apparatuses including memory cells and related methods
#683Two dimension material fin sidewall
#684Fin-type field-effect transistor device having substrate with heavy doped and light doped regions, and method of fabricating the same
#685Fabricating method of transistor structure
#686Quantum dot devices
#687Gate cut and fin trim isolation for advanced integrated circuit structure fabrication
#688Method of fabrication of a semiconductor device including one or more nanostructures
#689Semiconductor device and method of manufacturing the same
#690FinFETs having step sided contact plugs and methods of manufacturing the same
#691Semiconductor device
#692Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer
#693Methods of forming doped source/drain contacts and structures formed thereby
#694Semiconductor structure
#695Middle of line structures
#696Physically unclonable function device, method and apparatus
#697Semiconductor device with self-aligned wavy contact profile and method of forming the same
#698Method for epitaxial growth and device
#699Gate-all-around (GAA) method and devices
#700Method of manufacturing semiconductor device
#701Fin field effect transistor (FinFET) device and method for forming the same
#702Approach to high-k dielectric feature uniformity
#703Method for making semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance
#704Method for making semiconductor device including body contact dopant diffusion blocking superlattice to reduce contact resistance
#705Semiconductor apparatus
#706Semiconductor device and method of manufacture
#707Flat STI surface for gate oxide uniformity in Fin FET devices
#708Multi-gate device and method of fabrication thereof
#709Structure and method for FinFET device with contact over dielectric gate
#710Structure of a fin field effect transistor (FinFET)
#711Gate structure of field effect transistor with footing
#712Forming replacement low-k spacer in tight pitch fin field effect transistors
#713Field effect transistor with controllable resistance
#714Integrated assemblies having ferroelectric transistors with heterostructure active regions
#715Hybrid scheme for improved performance for P-type and N-type FinFETs
#716Semiconductor device and method of forming the semiconductor device
#717Integrated semiconductor processing
#718Method for forming semiconductor device structure with cap layer
#719Gate structure and method with enhanced gate contact and threshold voltage
#720Semiconductor device and manufacturing method thereof
#721Semiconductor device and method of manufacturing the same
#722Semiconductor device with epitaxial source/drain
#723Transistors with high concentration of germanium
#724Semiconductor device
#725Semiconductor device
#726Lattice-mismatched semiconductor substrates with defect reduction
#727Semiconductor device and manufacturing method thereof
#728Semiconductor arrangement and method of manufacture
#729One-transistor DRAM cell device having quantum well structure
#730Epi semiconductor material structures in source/drain regions of a transistor device formed on an SOI substrate
#731Integrated circuit with a fin and gate structure and method making the same
#732Source/drain feature to contact interfaces
#733Multi-gate device and method of fabrication thereof
#734Enhanced channel strain to reduce contact resistance in NMOS FET devices
#735Semiconductor device and method for fabricating the same
#736Method of manufacturing a semiconductor device and a semiconductor device
#737Semiconductor structure including isolations
#738Semiconductor device and method of forming the same
#739FinFET device and method of forming
#740Reducing gate-induced-drain-leakage current in a transistor by forming an enhanced band gap layer at the channel-to-drain interface
#741Method of forming the gate electrode of field effect transistor
#742Spacer structure with high plasma resistance for semiconductor devices
#743Semiconductor device with air-spacer
#744Selective germanium P-contact metalization through trench
#745Dual nitride stressor for semiconductor device and method of manufacturing
#746Techniques providing metal gate devices with multiple barrier layers
#747Field effect transistor contact with reduced contact resistance
#748Source/drain regions in fin field effect transistors (finFETs) and methods of forming same
#749Semiconductor device layout
#750Source/drain features with an etch stop layer
#751Semiconductor epitaxy bordering isolation structure
#752Method for fabricating a strained structure and structure formed
#753Field effect transistor contact with reduced contact resistance using implantation process
#754Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regions
#755MOS device with island region
#756Advanced wafer bonded heterojunction bipolar transistors and methods of manufacture of advanced wafer bonded heterojunction bipolar transistors
#757Vertical fin type bipolar junction transistor (BJT) device with a self-aligned base contact
#758Gate Stacks for Stack-Fin Channel I/O Devices and Nanowire Channel Core Devices
#759Semiconductor device and method of manufacturing the same
#760Mechanism for manufacturing semiconductor device
#761Devices including gate spacer with gap or void and methods of forming the same
#762Asymmetric threshold voltage VTFET with intrinsic dual channel epitaxy
#763Asymmetric threshold voltage VTFET with intrinsic dual channel epitaxy
#764Fin field effect transistor (FinFET) device structure with hard mask layer over gate structure and method for forming the same
#765Semiconductor device and method for manufacturing the same
#766Contact over active gate structures for advanced integrated circuit structure fabrication
#767Reducing parasitic capacitance for gate-all-around device by forming extra inner spacers
#768Etch stop layer for use in forming contacts that extend to multiple depths
#769Method for fabricating semiconductor structure
#770Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers
#771Gate-all-around integrated circuit structures having vertically discrete source or drain structures
#772Strained tunable nanowire structures and process
#773Method of manufacturing a semiconductor device and a semiconductor device
#774Different isolation liners for different type FinFETs and associated isolation feature fabrication
#775Multi-gate device
#776Source/drain recess in a semiconductor device
#777Semiconductor devices and methods of fabricating the same
#778Semiconductor device and manufacturing method thereof
#779Semiconductor device and method for forming the same
#780Extension region for a semiconductor device
#781Method semiconductor device fabrication with improved epitaxial source/drain proximity control
#782Method of manufacturing FinFETs having barrier layers with specified SiGe doping concentration
#783Metal gate scheme for device and methods of forming
#784Method to induce strain in finFET channels from an adjacent region
#785Dopant concentration boost in epitaxially formed material
#786Method of fabricating semiconductor device
#787Anti-fuse with reduced programming voltage
#788Metal gate stack having TaAlCN layer
#789Semiconductor device with fin and related methods
#790Method for depositing a group IV semiconductor and related semiconductor device structures
#791Silicon germanium alloy fins with reduced defects
#792Thin film cap to lower leakage in low band gap material devices
#793Intelligent semiconductor device having SiGe quantum well
#794Method for source/drain contact formation in semiconductor devices using common doping and common etching to n-type and p-type source/drains
#795Method for source/drain contact formation in semiconductor devices
#796Semiconductor structure
#797Spacers for nanowire-based integrated circuit device and method of fabricating same
#798Semiconductor device and method for manufacturing the same
#799Semiconductor method and device
#800Sub-fin leakage control in semicondcutor devices
#801Orientation engineering in complementary metal oxide semiconductor fin field effect transistor integration for increased mobility and sharper junction
#802Structure and method for semiconductor device
#803Integrating silicon-BJT to a silicon-germanium-HBT manufacturing process
#804Method for forming contact plug
#805Semiconductor devices
#806FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth
#807Single crystalline extrinsic bases for bipolar junction structures
#808Method for forming semiconductor device structure with inner spacer layer
#809Flexible merge scheme for source/drain epitaxy regions
#810Fin-like field effect transistor (FinFET) device and method of manufacturing same
#811Self-aligned vertical fin field effect transistor with replacement gate structure
#812Semiconductor Structures Which Include Laminates of First and Second Regions, and Methods of Forming Semiconductor Structures
#813Semiconductor devices with depleted heterojunction current blocking regions
#814Structure and formation method of semiconductor device with monoatomic etch stop layer
#815Circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation, and related methods
#816Semiconductor device having tipless epitaxial source/drain regions
#817Method of forming MOSFET structure
#818Gate spacer and method of forming
#819Semiconductor device and manufacturing method thereof
#820Integrated resistor for semiconductor device
#821Shared contact trench comprising dual silicide layers and dual epitaxial layers for source/drain layers of NFET and PFET devices
#822Shared contact trench comprising dual silicide layers and dual epitaxial layers for source/drain layers of NFET and PFET devices
#823Method for reducing contact resistance in semiconductor structures
#824Structure and method for SRAM FinFET device
#825SEMICONDUCTOR DEVICE
#826Semiconductor device having source and drain in active region and manufacturing method for same
#827Method of manufacturing a semiconductor device and a semiconductor device
#828Semiconductor device with gate-all-around (GAA) FETs having inner insulating spacers
#829IC including standard cells and SRAM cells
#830Stacked Gate-All-Around FinFET and method forming the same
#831Method of manufacturing semiconductor devices having a SiGe epitaxtial layer containing Ga
#832Semiconductor device and manufacturing method thereof
#833Semiconductor device and manufacturing method thereof
#834Heterogeneous metal line compositions for advanced integrated circuit structure fabrication
#835Field-effect transistors with a grown silicon-germanium channel
#836Semiconductor device and method
#837Vertical transistors with different gate lengths
#838Vertical transistors with different gate lengths
#839Semiconductor device and method of fabricating the same
#840Fin-type field-effect transistor device and method of fabricating the same
#841Selective film growth for bottom-up gap filling
#842Staggered-type tunneling field effect transistor
#843Staggered-type tunneling field effect transistor
#844Semiconductor device and manufacturing method thereof
#845MOS devices having epitaxy regions with reduced facets
#846Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions
#847Methods for forming recesses in source/drain regions and devices formed thereof
#848FinFET semiconductor device with germanium diffusion over silicon fins
#849Semiconductor device with source/drain contact formed using bottom-up deposition
#850Method of making FinFET CMOS device including single diffusion break in each of NMOS and PMOS regions
#851Method for manufacturing a FinFET device
#852Semiconductor quantum dot device and method for forming a scalable linear array of quantum dots
#853SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
#854Trench contact structures for advanced integrated circuit structure fabrication
#855Semiconductor device including multiple layers of memory cells, method of manufacturing the same, and electronic device including the same
#856Semiconductor device, method of manufacturing the same, and electronic device including the device
#857Etch-stop layer topography for advanced integrated circuit structure fabrication
#858Method to induce strain in 3-D microfabricated structures
#859Method to reduce etch variation using ion implantation
#860Semiconductor device and manufacturing method thereof
#861FinFET structures and methods of forming the same
#862Method for forming semiconductor device structure having oxide layer
#863Staggered-type tunneling field effect transistor
#864Staggered-type tunneling field effect transistor
#865Integrated circuit device fins
#866Fin cut and fin trim isolation for advanced integrated circuit structure fabrication
#867Spacer structure with high plasma resistance for semiconductor devices
#868Heterojunction bipolar transistor with counter-doped collector region and method of making same
#869Semiconductor device having a shaped epitaxial region
#870Interfacial layer between fin and source/drain region
#871SiGe heterojunction bipolar transistor with crystalline raised base on germanium etch stop layer
#872Method for increasing germanium concentration of FIN and resulting semiconductor device
#873Gate spacer and methods of forming
#874Integrated circuit structures having germanium-based channels
#875SOURCE OR DRAIN STRUCTURES WITH RELATIVELY HIGH GERMANIUM CONTENT
#876High surface dopant concentration formation processes and structures formed thereby
#877Semiconductor devices having different numbers of stacked channels in different regions and methods of manufacturing the same
#878Nonplanar device and strain-generating channel dielectric
#879Nanowire transistor structure and method of shaping
#880Method and device having low contact resistance
#881Semiconductor devices having stressed active regions therein and methods of forming same
#882Semiconductor devices
#883Semiconductor device and method of manufacturing the same
#884Self aligned top extension formation for vertical transistors
#885METHODS OF FORMING A BIPOLAR TRANSISTOR HAVING A COLLECTOR WITH A DOPING SPIKE
#886Field effect transistor contact with reduced contact resistance using implantation process
#887Interfacial layer between fin and source/drain region
#888Gate contact structure for a transistor
#889Orientation engineering in complementary metal oxide semiconductor fin field effect transistor integration for increased mobility and sharper junction
#890Orientation engineering in complementary metal oxide semiconductor fin field effect transistor integration for increased mobility and sharper junction
#891Embedded source/drain structure for tall FinFet and method of formation
#892Method for fabricating transistor with thinned channel
#893Structure and method for FinFET device with contact over dielectric gate
#894Vertical transistor with reduced gate length variation
#895Methods for forming recesses in source/drain regions and devices formed thereof
#896Semiconductor device including an active pattern having a lower pattern and a pair of channel patterns disposed thereon and method for manufacturing the same
#897Power reduction in finFET structures
#898Active matrix OLED display with normally-on thin-film transistors
#899Passivated and faceted for fin field effect transistor
#900Method for manufacturing semiconductor device