Semiconductor structure and manufacturing method thereof

Finfet semiconductor device structure with capped source drain structures

VERTICAL FINFET WITH IMPROVED TOP SOURCE/DRAIN CONTACT

Semiconductor device with high-quality epitaxial layer and method of manufacturing the same

Semiconductor device and manufacturing method thereof

FinFET device and method of forming same

Semiconductor structure with protection layer and fabrication method thereof

Self-aligned epitaxy layer

Silicide implants

NANOWIRE DEVICE WITH REDUCED PARASITICS

Semiconductor structure and fabrication method thereof

Memory devices including memory cells and related methods

Hybrid scheme for improved performance for P-type and N-type FinFETs

Structure and formation method of semiconductor device structure with isolation feature

Method for forming semiconductor device structure

Methods for depositing a doped germanium tin semiconductor and related semiconductor device structures

High dose implantation for ultrathin semiconductor-on-insulator substrates

Semiconductor device and method of manufacturing the same

Semiconductor devices

Gate-all-around field-effect-transistor devices and fabrication methods thereof

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Quantum dot devices with multiple dielectrics around fins

Gate walls for quantum dot devices

Superlattice materials and applications

Quantum dot devices with strain control

Quantum dot devices with passive barrier elements in a quantum well stack between metal gates

Semiconductor device including metal-2 dimensional material-semiconductor contact

Lateral bipolar junction transistor with abrupt junction and compound buried oxide

Ambipolar synaptic devices

Semiconductor structure and fabrication method thereof

Source and drain stressors with recessed top surfaces

Cascode heterojunction bipolar transistors

Semiconductor Device and Method for Manufacturing the Semiconductor Device

Method of fabricating a semiconductor device with strained SiGe fins and a Si cladding layer

Fabrication of fin field effect transistor complementary metal-oxide-semiconductor devices with uniform hybrid channels

Semiconductor device including a Fin-FET and method of manufacturing the same

Liner-less contact metallization

Method for selectively depositing a Group IV semiconductor and related semiconductor device structures

Method for depositing a group IV semiconductor and related semiconductor device structures

Methods of manufacturing inner spacers in a gate-all-around (GAA) FET through multi-layer spacer replacement

Structure and formation method of semiconductor device structure with etch stop layer

Semiconductor device and manufacturing method thereof

High voltage transistor using buried insulating layer as gate dielectric

Anti-fuse with reduced programming voltage

Electrostatic discharge protection structure and fabrication method thereof

MOS devices having epitaxy regions with reduced facets

Bipolar semiconductor device with silicon alloy region in silicon well and method for making

ALIGNED PITCH-QUARTERED PATTERNING FOR LITHOGRAPHY EDGE PLACEMENT ERROR ADVANCED RECTIFICATION

High-quality, single-crystalline silicon-germanium films

Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer

Silicon germanium fin immune to epitaxy defect

Semiconductor device with multi-layered source/drain regions having different dopant concentrations and manufacturing method thereof

Gate stack structure and method for forming the same

Semiconductor device having interfacial layer and high κ dielectric layer

Sidewall image transfer nanosheet

Enhanced channel strain to reduce contact resistance in NMOS FET devices

FinFET CMOS device including single diffusion break in each of NMOS and PMOS regions

Semiconductor structure with doped layers on fins and fabrication method thereof

Semiconductor devices, FinFET devices, and manufacturing methods thereof

Metal gate stack having TaAlCN layer

Crystallized silicon carbon replacement material for NMOS source/drain regions

Methods of forming a bulk field effect transistor (FET) with sub-source/drain isolation layers and the resulting structures

Semiconductor devices including a dummy gate structure on a fin

Substrate isolation for low-loss radio frequency (RF) circuits

SiGe source/drain structure

Semiconductor device and method of fabricating the same

Semiconductor device including a first fin active region and a second fin active region

Semiconductor device having a shaped epitaxial region

Semiconductor structure and fabrication method thereof

Trench-gated heterostructure and double-heterostructure active devices

Lateral fin static induction transistor

Vertical transistor gated diode

FINFET DEVICE WITH STACKED GERMANIUM AND SILICON CHANNEL

Source and drain epitaxy re-shaping

Semiconductor devices and methods of manufacturing the same

FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation

Silicon germanium fin immune to epitaxy defect

Forming strained channel with germanium condensation

Semiconductor devices

Digital alloy vertical lamellae FinFET with current flow in alloy layer direction

Semiconductor device and method for fabricating the same

Free-standing substrate comprising polycrystalline group 13 element nitride and light-emitting element using same

Semiconductor device and manufacturing method thereof

FinFET device with high-k metal gate stack

Method and structure of stacked FinFET

High pressure low thermal budge high-k post annealing process

Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process

Semiconductor devices with core-shell structures

Method of manufacturing a semiconductor device with multilayered channel structure

Gate structure of field effect transistor with footing

Method of forming improved vertical FET process with controlled gate length and self-aligned junctions

Metal gate and contact plug design and method forming same

Free-standing substrate comprising polycrystalline group 13 element nitride and light-emitting element using same

Method for semiconductor device fabrication with improved source drain proximity

Decoupling capacitor on strain relaxation buffer layer

Fabrication of fin field effect transistors for complementary metal oxide semiconductor devices including separate n-type and p-type source/drains using a single spacer deposition

Semiconductor epitaxy bordering isolation structure

Lattice-mismatched semiconductor substrates with defect reduction

Lattice-mismatched semiconductor substrates with defect reduction

Semiconductor device and manufacturing method thereof

Unipolar spacer formation for finFETs

Spacers for nanowire-based integrated circuit device and method of fabricating same

Transistor devices having source/drain structure configured with high germanium content portion

Two dimension material fin sidewall

Two dimension material fin sidewall

Method and device having low contact resistance

Device and fabrication of MOS device with island region

Systems and methods for a semiconductor structure having multiple semiconductor-device layers

Semiconductor devices with shaped portions of elevated source/drain regions

Self aligned top extension formation for vertical transistors

Threshold adjustment for quantum dot array devices with metal source and drain

Nanosheet transistors on bulk material

Method to induce strain in finFET channels from an adjacent region

Fabrication of fin field effect transistor complementary metal-oxide-semiconductor devices with uniform hybrid channels

Methods of fabricating semiconductor devices using MOS transistors with nonuniform gate electrode structures

Self-aligned contact process enabled by low temperature

Semiconductor device with chlorine-containing N-work function conductor and method of forming the same

Method of making a CMOS semiconductor device using a stressed silicon-on-insulator (SOI) wafer

Method for manufacturing a bipolar junction transistor

FinFET with epitaxial source and drain regions and dielectric isolated channel region

Semiconductor structures and fabrication methods thereof

Integration of strained silicon germanium PFET device and silicon NFET device for finFET structures

STI-diode structure

Dual threshold voltage (VT) channel devices and their methods of fabrication

Semiconductor device and method of fabricating the same

Field-effect semiconductor device having a heterojunction contact

Substrate isolation for low-loss radio frequency (RF) circuits

Structure and formation method of fin-like field effect transistor

Semiconductor devices and fabrication methods thereof

Source/drain recess in a semiconductor device

Vertical tunneling FinFET

Co-integration of tensile silicon and compressive silicon germanium

Dual channel silicon/silicon germanium complementary metal oxide semiconductor performance with interface engineering

A METHOD OF MANUFACTURING AN ARRAY SUBSTRATE AND A DISPLAY SUBSTRATE, AND A DISPLAY PANEL

EMBEDDED SIGE PROCESS FOR MULTI-THRESHOLD PMOS TRANSISTORS

Semiconductor device and method of manufacturing the same

Structure of semiconductor device structure having fins

Method of forming semiconductor device

Flexible merge scheme for source/drain epitaxy regions

Semiconductor structure and manufacturing method thereof

Semiconductor device and manufacturing method thereof

Gate fill utilizing replacement spacer

Active matrix OLED display with normally-on thin-film transistors

Active matrix OLED display with normally-on thin-film transistors

Electrical devices making use of counterdoped junctions

Semiconductor devices

Deep gate-all-around semiconductor device having germanium or group III-V active layer

Multi-gate device

Semiconductor device and method of forming the same

Tunneling field effect transistor (TFET) having a semiconductor fin structure

FinFET having improved Ge channel interfacial layer

Semiconductor structure and fabrication method thereof

Field effect transistor having a Fermi filter between a source and source contact thereof

Nanosheet transistor with uniform effective gate length

Semiconductor devices and methods of manufacturing the same

Two dimension material fin sidewall

Two dimension material fin sidewall

Two dimension material fin sidewall

Formation method and structure semiconductor device with source/drain structures

Methods of forming epi semiconductor material on a recessed fin in the source/drain regions of a FinFET device

Semiconductor structure and fabrication method thereof

Self-aligned bipolar junction transistors with a base grown in a dielectric cavity

PRESERVING THE SEED LAYER ON STI EDGE AND IMPROVING THE EPITAXIAL GROWTH

LDD-free semiconductor structure and manufacturing method of the same

Semiconductor device and method of forming the semiconductor device

Method of fabricating semiconductor device

Semiconductor device and method

Nanowire semiconductor device having high-quality epitaxial layer and method of manufacturing the same

Single-electron transistor with self-aligned coulomb blockade

Transistor device

Semiconductor device structure with gate spacer having protruding bottom portion and method for forming the same

Multi-gate devices with replaced-channels and methods for forming the same

Transmitting multi-destination packets in overlay networks

Methods of forming doped source/drain contacts and structures formed thereby

Semiconductor structure and fabrication method thereof

METHOD OF MAKING A SEMICONDUCTOR DEVICE USING A DUMMY GATE

Forming bottom isolation layer for nanosheet technology

Strain compensation in transistors

Forming horizontal bipolar junction transistor compatible with nanosheets

Fin field effect transistor and fabrication method thereof

Stacked gate-all-around FinFET and method forming the same

Semiconductor device including fin structure with two channel layers and manufacturing method thereof

Semiconductor device including fin structures and manufacturing method thereof

Vertical transistor with reduced gate-induced-drain-leakage current

Nanosheet MOSFET with partial release and source/drain epitaxy

Methods of forming backside self-aligned vias and structures formed thereby

Germanium dual-fin field effect transistor

Heterojunction bipolar transistor with a thickened extrinsic base

Forming non-line-of-sight source drain extension in an NMOS FINFET using n-doped selective epitaxial growth

Low resistance source drain contact formation

Nanosheet transistors with sharp junctions

Embedded SiGe epitaxy test pad

Methods for producing low oxygen silicon ingots

Semiconductor arrangement with substrate isolation

Co-fabricated gate-all-around field effect transistor and fin field effect transistor

Integrated circuit device and method of manufacturing the same

Semiconductor device and method for manufacturing the same

Nanosheet transistors on bulk material

Self-aligned sacrificial epitaxial capping for trench silicide

Methods of manufacturing semiconductor devices

Graphene contacts on source/drain regions of FinFET devices

Semiconductor device with low band-to-band tunneling

Metal gate scheme for device and methods of forming

Semiconductor device and method of fabricating the same

Wrap-around contact on FinFET

Methods for forming wrap around contact

Method for manufacturing a semiconductor device including a pair of channel semiconductor patterns

Low temperature polysilicon array substrate and method for manufacturing the same

Semiconductor device having fin-shaped structure and bump

Semiconductor device

Semiconductor device including quantum wires

Lateral PiN diodes and schottky diodes

Semiconductor structure and fabrication method thereof

Field effect transistor with channel layer, and semiconductor device including the same

Co-integration of elastic and plastic relaxation on the same wafer

SEMICONDUCTOR DEVICES INCLUDING VARIED DEPTH RECESSES FOR CONTACTS

Self-aligned doping in source/drain regions for low contact resistance

Self-aligned doping in source/drain regions for low contact resistance

Semiconductor devices having FIN active regions

Method of forming a fin structure of semiconductor device

Fin spacer protected source and drain regions in FinFETs

Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regions

Method of forming a contact structure for a FinFET semiconductor device

Method of manufacturing SOI lateral Si-emitter SiGe base HBT

Devices with strained source/drain structures and method of forming the same

Method and structure for protecting gates during epitaxial growth

Asymmetric band gap junctions in narrow band gap MOSFET

Semiconductor device and manufacturing method thereof

Semiconductor structure having insulator pillars and semiconductor material on substrate

Process for fabricating a field effect transistor having a coating gate

Precise junction placement in vertical semiconductor devices using etch stop layers

Semiconductor device and method of manufacturing semiconductor device

Fin field effect transistor complementary metal oxide semiconductor with dual strained channels with solid phase doping

Semiconductor device and method of fabricating the same

Device with diffusion blocking layer in source/drain region

Soi FinFET fins with recessed fins and epitaxy in source drain region

High pressure low thermal budge high-k post annealing process

Bipolar junction transistors with a combined vertical-lateral architecture

Conformal transfer doping method for fin-like field effect transistor

FinFET structures and methods of forming the same

Source and drain formation technique for fin-like field effect transistor

Semiconductor devices with multi-gate structure and method of manufacturing the same

Fin-like field effect transistor (FinFET) device and method of manufacturing same

Preparation method for heterogeneous SiGe based plasma P-I-N diode string for sleeve antenna

Structure and formation method of semiconductor device structure

FinFET devices and methods of forming

FinFET structures and methods of forming the same

Nanowire field effect transistor having a metal gate surrounding semiconductor nanowire

Semiconductor device and method of forming doped channel thereof

Method for reducing contact resistance in semiconductor structures

N-type fin field-effect transistor

Method for manufacturing semiconductor structure

Method for forming recess within epitaxial layer

Semiconductor structure and fabricating method thereof

Lateral bipolar junction transistor with controlled junction

Silicon Carbide Vertical MOSFET with Polycrystalline Silicon Channel Layer

Method of forming fin shape structure having different buffer layers

Methods for titanium silicide formation using TiClprecursor and silicon-containing precursor

Method of forming semiconductor device using titanium-containing layer and device formed

Method and structure for incorporating strain in nanosheet devices

SiGe source/drain structure and preparation method thereof

Field-effect transistor

Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions

Semiconductor device and method for fabricating the same

Mechanisms for growing epitaxy structure of finFET device

Methods of fabricating semiconductor devices

Method of removing an etch mask

Semiconductor device and manufacturing method thereof

CARBON-BASED INTERFACE FOR EPITAXIALLY GROWN SOURCE/DRAIN TRANSISTOR REGIONS

RESISTANCE REDUCTION IN TRANSISTORS HAVING EPITAXIALLY GROWN SOURCE/DRAIN REGIONS

Elongated source/drain region structure in finFET device

Dopant concentration boost in epitaxially formed material

Method of manufacturing a semiconductor device with multilayered channel structure

FinFET device and methods of forming

Semiconductor device manufacturing method with reduced gate electrode height loss and related devices

Semiconductor device having two spacers

Superlattice materials and applications

Semiconductor device having asymmetrical source/drain

Semiconductor device and forming method thereof

Semiconductor structure, static random access memory, and fabrication method thereof

Semiconductor structure, static random access memory and fabrication method thereof

Method of manufacturing a semiconductor device and a semiconductor device

Conductive structure and method for manufacturing conductive structure

FinFET device having oxide layer among interlayer dielectric layer

FinFET device and method of forming

Multi-gate device and method of fabrication thereof

Source/drain structure having multi-facet surfaces

Techniques for integration of Ge-rich p-MOS source/drain

Metal gate scheme for device and methods of forming

Fin field effect transistors having conformal oxide layers and methods of forming same

Silicon on insulator device with partially recessed gate

Fully substrate-isolated FinFET transistor

Deposition apparatus and method for manufacturing semiconductor device using the same

Semiconductor device and forming method thereof

Semiconductor device and method for fabricating the same

FIELD EFFECT TRANSISTOR INCLUDING GRAPHENE LAYER

Semiconductor structures having increased channel strain using fin release in gate regions

Nanostructure field-effect transistors with enhanced mobility source/drain regions

Integrated RF front end system

Vertical Thyristor Cell and Memory Array with Silicon Germanium Base Regions