Fin field effect transistor (FinFET) device structure

FORMING DEFECT-FREE RELAXED SiGe FINS

Superlattice lateral bipolar junction transistor

Nanolaminate structure, semiconductor device and method of forming nanolaminate structure

Semiconductor device and method for fabricating the same

Method for fabricating a local interconnect in a semiconductor device

Forming a contact for a semiconductor device

Self aligned top extension formation for vertical transistors

Methods of simultaneously forming bottom and top spacers on a vertical transistor device

Nanosheet transistors with sharp junctions

Semiconductor device having fin-type patterns

Formation of FinFET junction

Approach to minimization of strain loss in strained fin field effect transistors

Forming strained channel with germanium condensation

Handle for semiconductor-on-diamond wafers and method of manufacture

Approach to minimization of strain loss in strained fin field effect transistors

Process for fabricating a field effect transistor having a coating gate

IC unit and methond of manufacturing the same, and electronic device including the same

Method for manufacturing a semiconductor device having a fin located on a substrate

Transistor with an airgap for reduced base-emitter capacitance and method of forming the transistor

FinFET with a semiconductor strip as a base

FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth

METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE

Semiconductor device

Semiconductor device, method of manufacturing the same and electronic device including the same

Method for fabricating FinFet

Semiconductor device, method of manufacturing the same and electronic device including the device

FinFET device with abrupt junctions

Semiconductor devices and methods of manufacturing semiconductor devices

Fabrication of silicon germanium-on-insulator FinFET

Multi-gate device and method of fabrication thereof

Semiconductor device blocking leakage current and method of forming the same

Tensile strained NFET and compressively strained PFET formed on strain relaxed buffer

Semiconductor device and method for fabricating the same

Semiconductor devices including active areas with increased contact area

Semiconductor device and method of forming the semiconductor device

Semiconductor device and manufacturing method thereof

Forming a fin cut in a hardmask

Polysilicon residue removal in nanosheet MOSFETs

Method of manufacturing SOI lateral Si-emitter SiGe base HBT

Method of junction control for lateral bipolar junction transistor

Method of junction control for lateral bipolar junction transistor

Methods of forming bottom and top source/drain regions on a vertical transistor device

Semiconductor device with epitaxial source/drain

FinFETs with strained well regions

FETS and methods of forming FETS

FinFET with reduced series total resistance

Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process

METHOD OF CONTACT FORMATION BETWEEN METAL AND SEMICONDUCTOR

Epitaxial and silicide layer formation at top and bottom surfaces of semiconductor fins

Asymmetric band gap junctions in narrow band gap MOSFET

Structure and method for semiconductor device

Techniques providing metal gate devices with multiple barrier layers

Nonplanar device and strain-generating channel dielectric

MOS devices having epitaxy regions with reduced facets

Semiconductor device

Method to induce strain in 3-D microfabricated structures

Semiconductor device and manufacturing method thereof

Semiconductor device including a fin structure

Fabrication of integrated circuit structures for bipolar transistors

Forming non-line-of-sight source drain extension in an NMOS FINFET using n-doped selective epitaxial growth

Method of forming the gate electrode of field effect transistor

Fabrication of fin field effect transistors for complementary metal oxide semiconductor devices including separate n-type and p-type source/drains using a single spacer deposition

Leakage current suppression methods and related structures

FETs and methods for forming the same

Fabrication of semiconductor device

Structure and method for integrated circuit

Method for producing a doped semiconductor layer

Semiconductor device structure with self-aligned capacitor device

Substrate contact land for an MOS transistor in an SOI substrate, in particular an FDSOI substrate

Method of forming source/drain contact

Strained silicon complementary metal oxide semiconductor including a silicon containing tensile n-type fin field effect transistor and silicon containing compressive p-type fin field effect transistor formed using a dual relaxed substrate

Reacted conductive gate electrodes and methods of making the same

Fabrication of vertical fin transistor with multiple threshold voltages

Fabrication of vertical fin transistor with multiple threshold voltages

Fabrication of vertical fin transistor with multiple threshold voltages

LDMOS transistor structures and integrated circuits including LDMOS transistor structures

Semiconductor device and method for fabricating the same

Field effect transistor contact with reduced contact resistance

Tensile strained high percentage silicon germanium alloy FinFETS

Method for fabricating transistor with thinned channel

Structure and method for forming strained FinFET by cladding stressors

Techniques for forming non-planar germanium quantum well devices

Bipolar junction transistor (BJT) base conductor pullback

Hybrid source and drain contact formation using metal liner and metal insulator semiconductor contacts

FINFETs with wrap-around silicide and method forming the same

Semiconductor structure and fabricating method thereof

Methods for manufacturing a fin-based semiconductor device including a metal gate diffusion break structure with a conformal dielectric layer

Co-integration of self-aligned and non-self aligned heterojunction bipolar transistors

Semiconductor device and method

Integrated circuits having source/drain structure

Forming a non-planar transistor having a quantum well channel

Methods of forming IC products comprising a nano-sheet device and a transistor device having first and second replacement gate structures

Methods of forming NMOS and PMOS finFET devices and the resulting product

Isolation structure of semiconductor device

Semiconductor device and manufacturing method thereof

Semiconductor device with fin and related methods

High acceptor level doping in silicon germanium

Power semiconductor device

Silicon-germanium Fin structure having silicon-rich outer surface

Fabrication of silicon-germanium fin structure having silicon-rich outer surface

FETS and methods of forming FETS

Precleaning apparatus and substrate processing system

Tunneling transistor and method of fabricating the same

Method for reducing contact resistance in semiconductor structures

Lateral bipolar junction transistor with controlled junction

Semiconductor devices having 3D channels, and methods of fabricating semiconductor devices having 3D channels

Semiconductor devices with depleted heterojunction current blocking regions

Individually-tunable heat reflectors in an EPI-growth system

Source and drain stressors with recessed top surfaces

FinFETs with source/drain cladding

Anti-fuse with reduced programming voltage

Semiconductor structure with self-aligned wells and multiple channel materials

Semiconductor device including optimized elastic strain buffer

Method of manufacturing semiconductor device

Tunneling field effect transistor

Formation of dislocations in source and drain regions of FinFET devices

Biosensor based on heterojunction bipolar transistor

FORMING A SILICON BASED LAYER IN A TRENCH TO PREVENT CORNER ROUNDING

FinFETs with strained well regions

Semiconductor structure and method for semiconductor device fabrication with improved source drain epitaxy

Asymmetric FET

Selective germanium p-contact metalization through trench

Method and structure for FinFET device

Device for a FinFET

DIODES AND FABRICATION METHODS THEREOF

Precise junction placement in vertical semiconductor devices using etch stop layers

Semiconductor device including Fin-PET and manufacturing method thereof

Field-effect transistor and method of making the same

Fabrication of integrated circuit structures for bipolor transistors

Integration of strained silicon germanium PFET device and silicon NFET device for finFET structures

Multigate metal-oxide semiconductor field effect transistor

III-V compound semiconductor channel post replacement gate

Strained silicon complementary metal oxide semiconductor including a silicon containing tensile N-type fin field effect transistor and silicon containing compressive P-type fin field effect transistor formed using a dual relaxed substrate

Methods of forming a bipolar transistor having a collector with a doping spike

Strained channel field effect transistor

Methods for forming hybrid vertical transistors

Semiconductor device having silicon-germanium source/drain regions with varying germanium concentrations

Single electron transistor with self-aligned Coulomb blockade

Embedded shape sige for strained channel transistors

Semiconductor device structure with fin structure and method for forming the same

Semiconductor devices including contact structures that partially overlap silicide layers

Semiconductor device having contact plugs and method of forming the same

Semiconductor device and manufacturing method therefor

Semiconductor device structure and method for forming the same

FinFETs with strained well regions

Charge pump circuit with low reverse current and low peak current

Bottom-up epitaxy growth on air-gap buffer

Method for forming semiconductor structure

Method to form strained channel in thin box SOI structures by elastic strain relaxation of the substrate

FinFET structure and methods thereof

Semiconductor device and method for fabricating the same

Non-volatile memory and method for programming and reading a memory array having the same

Semiconductor devices including a dummy gate structure on a fin

Semiconductor device structure with gate stack and method for forming the same

Flat STI surface for gate oxide uniformity in Fin FET devices

Semiconductor device having tipless epitaxial source/drain regions

SOI FinFET fins with recessed fins and epitaxy in source drain region

Dummy dielectric fins for finFETs with silicon and silicon germanium channels

Dummy dielectric fins for finFETs with silicon and silicon germanium channels

Digital alloy vertical lamellae finfet with current flow in alloy layer direction

MOSFETs with channels on nothing and methods for forming the same

Semiconductor structure including a transistor having stress creating regions and method for the formation thereof

Source/drain junction formation

Process for fabricating a vertical-channel nanolayer transistor

Manufacturing method of semiconductor device

Devices and methods of forming self-aligned, uniform nano sheet spacers

Structure and method for SRAM FinFET device having an oxide feature

Semiconductor fabrication method including non-uniform cover layer

Method for forming semiconductor structure having stress layers

SOI WAFERS AND DEVICES WITH BURIED STRESSOR

Method of manufacturing semiconductor device

Semiconductor device and method for fabricating the same

Ambipolar synaptic devices

Semiconductor quantum dot device and method for forming a scalable linear array of quantum dots

Method for manufacturing a bipolar junction transistor

Source/drain recess volume trim for improved device performance and layout dependence

Gate structure having designed profile

Two-dimensional condensation for uniaxially strained semiconductor fins

Methods, apparatus, and system for improved nanowire/nanosheet spacers

Semiconductor device and method of manufacturing the same

Logic semiconductor devices

Etching method

Strained structure of a semiconductor device

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

N-work function metal with crystal structure

Hybrid source and drain contact formation using metal liner and metal insulator semiconductor contacts

Semiconductor device including a superlattice and replacement metal gate structure and related methods

Lateral bipolar junction transistor with abrupt junction and compound buried oxide

Lateral bipolar junction transistor with abrupt junction and compound buried oxide

Sub 59 MV/decade SI CMOS compatible tunnel FET as footer transistor for power gating

Methods of forming NMOS and PMOS FinFET devices and the resulting product

Structure and method for FinFET device

Directional deposition of protection layer

Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction

Semiconductor device including a field effect transistor and method for manufacturing the same

Fabrication of vertical fin transistor with multiple threshold voltages

Transistor having a monocrystalline connection

Semiconductor devices with germanium-rich active layers and doped transition layers

Semiconductor device and manufacturing method thereof

Method and IC structure for increasing pitch between gates

Extra gate device for nanosheet

Transistors incorporating metal quantum dots into doped source and drain regions

Passivated and faceted for fin field effect transistor

FinFET with a semiconductor strip as a base

Single process for liner and metal fill

Semiconductor device having stressor layer

Method for fabricating a semiconductor device having a first fin active pattern and a second fin active pattern

Methods for fin thinning providing improved SCE and S/D EPI growth

Semiconductor device and manufacturing method thereof

Semiconductor device having a graphene layer, and method of manufacturing thereof

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

Method for fabricating fin-shaped structure and bump made of different material

Method for forming semiconductor device structure

Semiconductor device and fabrication method therefor

Nanosheet and nanowire devices having source/drain stressors and methods of manufacturing the same

SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME

Transistor strain-inducing scheme

Semiconductor device and method of fabricating the same

Semiconductor devices including an isolation layer on a fin and methods of forming semiconductor devices including an isolation layer on a fin

Semiconductor structure having insulator pillars and semiconductor material on substrate

SEMICONDUCTOR DEVICE STRAIN RELAXATION BUFFER LAYER

MOS devices having epitaxy regions with reduced facets

Integrated circuit transistor structure with high germanium concentration SiGe stressor

Compound semiconductor device

Advanced wafer bonded heterojunction bipolar transistors and methods of manufacture of advanced wafer bonded heterojunction bipolar transistors

Semiconductor device strain relaxation buffer layer

Expitaxially regrown heterostructure nanowire lateral tunnel field effect transistor

Directional deposition of protection layer

Multi-gate device and method of fabrication thereof

Semiconductor device and manufacturing method thereof

Methods and structures to prevent sidewall defects during selective epitaxy

Semiconductor structure with etched fin structure

Fin field effect transistor (FinFET) device and method for forming the same

Fin-type field effect transistor structure and manufacturing method thereof

Sidewall image transfer nanosheet

Method, apparatus and system for improved nanowire/nanosheet spacers

Double aspect ratio trapping

FinFET structure device

Doping profile for strained source/drain region

Airgap spacers

Method for manufacturing transistor with SiCN/SiOCN multilayer spacer

Semiconductor devices including field effect transistors and methods of forming the same

Structure and method for semiconductor device

Method to improve HCI performance for FinFET

Methods of forming graphene contacts on source/drain regions of FinFET devices

Semiconductor device and method for manufacturing the same

Semiconductor device and method of manufacturing the same

FIN WITH AN EPITAXIAL CLADDING LAYER

Tunneling fin type field effect transistor with epitaxial source and drain regions

Self-aligned heterojunction field effect transistor

Device with diffusion blocking layer in source/drain region

Ionic barristor

FinFET devices having a material formed on reduced source/drain region

Tensile strained nFET and compressively strained pFET formed on strain relaxed buffer

Tensile strained nFET and compressively strained pFET formed on strain relaxed buffer

III-V semiconductor CMOS FinFET device

Vertical thyristor memory with minority carrier lifetime reduction

Strain relaxed buffer layers with virtually defect free regions

Enhanced dislocation stress transistor

Strained silicon germanium fin with block source/drain epitaxy and improved overlay capacitance

Method for semiconductor device fabrication with improved source drain proximity

Field effect transistor contact with reduced contact resistance

Method to improve device performance for FinFET

Bipolar junction transistors with extrinsic device regions free of trench isolation

Methods of manufacturing semiconductor devices by forming source/drain regions before gate electrode separation

Semiconductor device and method of fabricating the same

Method and structure for incorporating strain in nanosheet devices

Transistor structures and fabrication methods thereof

Low resistance source drain contact formation

Decoupling capacitor on strain relaxation buffer layer

Fin-double-gated junction field effect transistor

Decoupling capacitor on strain relaxation buffer layer

Semiconductor device with conductive pattern on insulating line pattern on spacer on field insulating film in trench between fin patterns

Active regions with compatible dielectric layers

Method for manufacturing a high-voltage FinFET device having LDMOS structure

Superlattice materials and applications

Method for fabricating a local interconnect in a semiconductor device

MOS devices with ultra-high dielectric constants and methods of forming the same

Manufacturing method of metal gate structure

PMOS transistor and fabrication method thereof

Semiconductor device having epitaxial layer with planar surface and protrusions

Semiconductor device having asymmetric active region and method of forming the same

Methods, apparatus and system for providing source-drain epitaxy layer with lateral over-growth suppression

Fins for metal oxide semiconductor device structures

Semiconductor device and manufacturing method thereof

Semiconductor devices and methods of manufacturing the same

Deep gate-all-around semiconductor device having germanium or group III-V active layer

High selectivity nitride removal process based on selective polymer deposition

Semiconductor device having NFET structure and method of fabricating the same

Transistors having strained channel under gate in a recess

High selectivity nitride removal process based on selective polymer deposition

Growth of semiconductors on hetero-substrates using graphene as an interfacial layer

V-shaped epitaxially formed semiconductor layer

Semiconductor devices including protruding insulation portions between active fins

Semiconductor device having field insulation layer between two fins

Stacked nanowires with multi-threshold voltage solution for PFETS

Electrostatic discharge protection structure and fabrication method thereof

Extra gate device for nanosheet

SEMICONDUCTOR DEVICE AND METHOD FOR FABRIACTING THE SAME