Semiconductor device including fin shaped structure including silicon germanium layer

Silicon germanium fin immune to epitaxy defect

Semiconductor device including an epitaxy region

Gate structure of field effect transistor with footing

Field effect transistor structure with abrupt source/drain junctions

Nanowire device with reduced parasitics

STRUCTURE AND METHOD FOR SiGe FIN FORMATION IN A SEMICONDUCTOR DEVICE

Formation method of semiconductor device structure

Non-silicon device heterolayers on patterned silicon substrate for CMOS by combination of selective and conformal epitaxy

Non-planar transistor

FinFETs with strained well regions

Methods for forming semiconductor device structures

Semiconductor devices with source/drain stress liner

Junction butting structure using nonuniform trench shape

Channel replacement and bimodal doping scheme for bulk finFet threshold voltage modulation with reduced performance penalty

High mobility transport layer structures for rhombohedral Si/Ge/SiGe devices

Superlattice lateral bipolar junction transistor

Strain compensation in transistors

Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon region

Enhanced channel strain to reduce contact resistance in NMOS FET devices

Method and device for reducing FinFET self-heating effect

Semiconductor device

Silicon germanium alloy fins with reduced defects

Source and drain stressors with recessed top surfaces

Silicon germanium alloy fins with reduced defects

Tall strained high percentage silicon germanium fins for CMOS

FINFET CMOS with Si NFET and SiGe PFET

FinFET CMOS with Si NFET and SiGe PFET

Semiconductor device and method for fabricating the same

Method for reducing loss of silicon cap layer over SiGe source/drain in a CMOS device

Semiconductor devices having high-quality epitaxial layer and methods of manufacturing the same

Semiconductor device including fin structure with two channel layers and manufacturing method thereof

Semiconductor device and manufacturing method thereof

Methods for fabricating semiconductor devices having fin-shaped patterns by selectively removing oxidized portions of the fin-shaped patterns

Gate spacer and methods of forming

Field effect transistor and semiconductor device including the same

Semiconductor device having germanium active layer with underlying diffusion barrier layer

Multi bit capacitorless DRAM and manufacturing method thereof

Semiconductor device having fin-type patterns

Ge/SiGe-channel and III-V-channel transistors on the same die

Semiconductor device and manufacturing method thereof

FinFET with epitaxial source and drain regions and dielectric isolated channel region

Method for forming semiconductor structure with epitaxial growth structure

Semiconductor device including a strain relief buffer

FETS and methods of forming FETS

Methods of forming silicon germanium tin films and structures and devices including the films

Method for fabricating a strained structure and structure formed

Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regions

Semiconductor device

Semiconductor devices with layers commonly contacting fins and methods of manufacturing the same

Dual channel material for finFET for high performance CMOS

Dual channel material for finFET for high performance CMOS

Stacked nanowire semiconductor device

Semiconductor device

FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF

FinFET with merged, epitaxial source/drain regions

Semiconductor device having an oxygen diffusion barrier

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

Source/drain regions for fin field effect transistors and methods of forming same

Semiconductor device and manufacturing method thereof

Semiconductor device with low band-to-band tunneling

Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs

FinFet spacer etch with no fin recess and no gate-spacer pull-down

Semiconductor device

Semiconductor device with low band-to-band tunneling

Silicon and silicon germanium nanowire structures

Fin sculpting and cladding during replacement gate process for transistor channel applications

Semiconductor device and manufacturing method thereof

Semiconductor structure and fabricating method thereof

Semiconductor devices having multiple gate structures and methods of manufacturing such devices

Semiconductor structure and manufacturing method thereof

Semiconductor device having metallic source and drain regions

Retaining strain in finFET devices

Semiconductor device and fabricating method of a gate with an epitaxial layer

Semiconductor device and fabrication method for forming the same

Fin field effect transistor complementary metal oxide semiconductor with dual strained channels with solid phase doping

Method of making a graphene base transistor with reduced collector area

Tunnel field effect transistors

Germanium tin channel transistors

GE and III-V channel semiconductor devices having maximized compliance and free surface relaxation

Method and apparatus providing improved thermal conductivity of strain relaxed buffer

Three-dimensional semiconductor memory devices including a vertical channel

Structure and method for compressively strained silicon germanium fins for pFET devices and tensily strained silicon fins for nFET devices

Semiconductor structures and fabrication methods thereof

Semiconductor device having a stacked fin structure and manufacturing method thereof

COMPACT MEMORY STRUCTURE INCLUDING TUNNELING DIODE

Semiconductor structure and manufacturing method thereof

Semiconductor device and fabrication method thereof

Semiconductor device and method of fabricating the same

Epitaxial structure of semiconductor device and manufacturing method thereof

Source/drain FinFET channel stressor structure

Conductor including nano-patterned substrate and method of manufacturing the conductor

Semiconductor liner of semiconductor device

Semiconductor device and method of fabricating the same

Semiconductor device and method of fabricating the same

Contact resistance reduction technique

Logic semiconductor devices

Semiconductor structure with enhanced contact and method of manufacture the same

Source/drain structure of a fin field effect transistor (FinFET)

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE CAPABLE OF REDUCING A LEAKAGE CURRENT

Semiconductor devices including insulating materials in fins

Method of fabricating semiconductor device

Method of evaluating semiconductor device and apparatus for evaluating semiconductor device

Semiconductor device including dual-layer source/drain region

METHOD AND APPARATUS FOR SOURCE-DRAIN JUNCTION FORMATION IN A FINFET WITH IN-SITU DOPING

Forming replacement low-K spacer in tight pitch fin field effect transistors

Semiconductor device and method for fabricating the same

FinFET semiconductor device with germanium diffusion over silicon fins

Semiconductor device including dual-layer source/drain region

Forming replacement low-K spacer in tight pitch fin field effect transistors

Semiconductor device and method for fabricating the same

Semiconductor device

Semiconductor structure and manufacturing method thereof

Field effect transistors and methods of forming same

Hybrid substrate engineering in CMOS finFET integration for mobility improvement

Semiconductor devices and methods of forming the same

Semiconductor structure and fabricating method thereof

Semiconductor devices including source/drain regions having multiple epitaxial patterns

Semiconductor devices having source/drain regions with strain-inducing layers and methods of manufacturing such semiconductor devices

Tensile strained high percentage silicon germanium alloy FinFETs

Multiple gate field effect transistors having oxygen-scavenged gate stack

Orientation engineering in complementary metal oxide semiconductor fin field effect transistor integration for increased mobility and sharper junction

Orientation engineering in complementary metal oxide semiconductor fin field effect transistor integration for increased mobility and sharper junction

Highly scaled tunnel FET with tight pitch and method to fabricate same

Method of fabricating a MOSFET with an undoped channel

Gap fill self planarization on post EPI

Semiconductor device with reduced poly spacing effect

Semiconductor devices including a dummy gate structure on a fin

Structure and formation method of semiconductor device structure

Highly scaled tunnel FET with tight pitch and method to fabricate same

Test structure, fabrication method, and test method

Amplifiers including tunable tunnel field effect transistor pseudo resistors and related devices

Semiconductor device and manufacturing method thereof

Epitaxial and silicide layer formation at top and bottom surfaces of semiconductor fins

FinFET device with vertical silicide on recessed source/drain epitaxy regions

FET with local isolation layers on S/D trench sidewalls

Dual-material mandrel for epitaxial crystal growth on silicon

FinFET memory device

Semiconductor device having first and second gate electrodes and method of manufacturing the same

FinFET contact structure and method for forming the same

Semiconductor device and manufacturing method thereof

Structure and formation method of fin-like field effect transistor

Asymmetric semiconductor device and method of forming same

FETS and methods of forming FETs

Method for causing tensile strain in a semiconductor film

Embedded SiGe process for multi-threshold PMOS transistors

FinFET device having a channel defined in a diamond-like shape semiconductor structure

Semiconductor device including epitaxially formed buried channel region

SEMICONDUCTOR DEVICE

Semiconductor device structure with gate spacer having protruding bottom portion and method for forming the same

Structure and formation method of fin-like field effect transistor

Formation of nickel silicon and nickel germanium structure at staggered times

Flat STI surface for gate oxide uniformity in Fin FET devices

METHOD OF FORMING SEMICONDUCTOR DEVICE

Semiconductor device including dual spacer and uniform epitaxial buffer interface of embedded SiGe source/drain

Semiconductor device including epitaxially formed buried channel region

Methods and systems for reducing dislocation defects in high concentration epitaxy processes

Semiconductor devices

Substrate resistor and method of making same

Semiconductor device including epitaxially formed buried channel region

Method for fabricating semiconductor device

Fin liner integration under aggressive pitch

Co-integration of tensile silicon and compressive silicon germanium

Non-planar quantum well device having interfacial layer and method of forming same

Strained finFET device fabrication

Semiconductor device and manufacturing method thereof

P-tunneling field effect transistor device with pocket

Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions

Strained finFET device fabrication

Semiconductor structures having increased channel strain using fin release in gate regions

Integrated structures containing vertically-stacked memory cells

Fully substrate-isolated FinFET transistor

Strained FinFET device fabrication

FinFET with source/drain structure and method of fabrication thereof

Semiconductor structures having increased channel strain using fin release in gate regions

Strained finFET device fabrication

Internal spacers for nanowire transistors and method of fabrication thereof

Semiconductor device including fin shaped structure and method for fabricating the same

Hybrid substrate engineering in CMOS finFET integration for mobility improvement

Fin-shaped field effect transistor

Integrated circuit structure with substrate isolation and un-doped channel

Method for fabricating semiconductor device

Contact resistance reduction employing germanium overlayer pre-contact metalization

Epitaxial and silicide layer formation at top and bottom surfaces of semiconductor fins

Semiconductor structure with multilayer III-V heterostructures

Semiconductor devices with germanium-rich active layers and doped transition layers

Hybrid substrate engineering in CMOS finFET integration for mobility improvement

Manufacturing method of semiconductor structure

Method for forming semiconductor device structure

Reduced local threshold voltage variation MOSFET using multiple layers of epi for improved device operation

Method of making a semiconductor device using a dummy gate

Method for fabricating substrate of semiconductor device including epitaxial layer and silicon layer having same crystalline orientation

Semiconductor device and method of fabricating the same

Gate-all-around nanowire device and method for manufacturing such a device

Semiconductor fin isolation by a well trapping fin portion

Semiconductor device including fin structures disposed over buffer structures and manufacturing method thereof

Semiconductor device including fin having condensed channel region

Fabricating method of a strained FET

SEMICONDUCTOR DEVICE INCLUDING FIN HAVING CONDENSED CHANNEL REGION

METHODS OF FORMING REPLACEMENT FINS COMPRISED OF MULTIPLE LAYERS OF DIFFERENT SEMICONDUCTOR MATERIALS

Semiconductor device having embedded strain-inducing pattern and method of forming the same

Bulk fin formation with vertical fin sidewall profile

Integrated circuit having strained fins on bulk substrate and method to fabricate same

Porous fin as compliant medium to form dislocation-free heteroepitaxial films

Systems and methods for graphene mechanical oscillators with tunable frequencies

Method of fabricating nanowire field effect transistor having a preplacement gate by using sacrificial etch layer

FinFET having an oxide region in the source/drain region

Dual-material mandrel for epitaxial crystal growth on silicon

Semiconductor device with a reduced band gap zone

FinFETs with multiple threshold voltages

Methods of fabricating semiconductor devices

Semiconductor device having a fin

Integrated RF front end system

Semiconductor devices having fin-type patterns and metal contacts and methods of manufacturing the same

Semiconductor device having a necked semiconductor body and method of forming semiconductor bodies of varying width

Semiconductor device and manufacturing method thereof

Semiconductor device with fin and related methods

Aspect ratio trapping (ART) for fabricating vertical semiconductor devices

Techniques for integration of Ge-rich p-MOS source/drain contacts

Germanium-based quantum well devices

Method and structure for FinFET device

Substrate contact land for an MOS transistor in an SOI substrate, in particular an FDSOI substrate

Low defect relaxed SiGe/strained Si structures on implant anneal buffer/strain relaxed buffer layers with epitaxial rare earth oxide interlayers and methods to fabricate same

Ambipolar synaptic devices

Semiconductor device and manufacturing method thereof

Multi-gate device and method of fabrication thereof

Bipolar transistor having collector with doping spike

Semiconductor devices

Sandwich EPI channel for device enhancement

FinFET devices and methods of forming

Method of forming fin structure of semiconductor device

Field effect transistors with strained channel features

Semiconductor device

Multiple gate field-effect transistors having oxygen-scavenged gate stack

Fin field effect transistor

Formation of strained fins in a finFET device

Fabrication of silicon germanium-on-insulator finFET

Strain compensation in transistors

Pulsed laser anneal process for transistor with partial melt of a raised source-drain

Low parasitic capacitance and resistance finFET device

FinFETs with strained well regions

Quantum well MOSFET channels having lattice mismatch with metal source/drains, and conformal regrowth source/drains

Semiconductor devices and methods of manufacturing the same

Method and apparatus providing improved thermal conductivity of strain relaxed buffer

Formation method of semiconductor device structure with cap element

Column IV transistors for PMOS integration

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Methods of fabricating semiconductor devices

Diodes and fabrication methods thereof

Semiconductor device including strained finFET

Formation of dislocation-free SiGe finFET using porous silicon

Semiconductor device including fin structures and manufacturing method thereof

Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process

TUNNEL FIELD EFFECT TRANSISTORS HAVING LOW TURN-ON VOLTAGE

Germanium dual-fin field effect transistor

Germanium dual-fin field effect transistor

Method for manufacturing a semiconductor device

Semiconductor device including strained finFET

Semiconductor device blocking leakage current and method of forming the same

Semiconductor device including spacers having different dimensions

Integrated Circuit On Corrugated Substrate

Semiconductor device having stressor and method of manufacturing the same

Germanium dual-fin field effect transistor

SiGe FinFET with improved junction doping control

Semiconductor device, method of manufacturing the same, and method of evaluating semiconductor device

High mobility strained channels for fin-based NMOS transistors

Methods for forming wrap around contact

PROCESS FOR PRODUCING MOS TRANSISTORS HAVING A LARGER CHANNEL WIDTH FROM AN SOI AND IN PARTICULAR FDSOI SUBSTRATE, AND CORRESPONDING INTEGRATED CIRCUIT

Aspect ratio for semiconductor on insulator

SEMICONDUCTOR DEVICES INCLUDING VARIED DEPTH RECESSES FOR CONTACTS

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Silicon-germanium fin formation

Semiconductor device and method of fabricating the same

Semiconductor devices having multiple gate structures and methods of manufacturing such devices

Method for manufacturing semiconductor device using high speed epitaxial lift-off and template for III-V direct growth and semiconductor device manufactured using the same

Semiconductor device including metal-2 dimensional material-semiconductor contact

Structure and method for FINFET device

Semiconductor devices having fins

Preserving the seed layer on STI edge and improving the epitaxial growth

Non-planar transistor and method of forming the same

Semiconductor device including field effect transistors

Method for improving transistor performance through reducing the salicide interface resistance

Method for improving transistor performance through reducing the salicide interface resistance

Tuning strain in semiconductor devices

Nonvolatile memory device using two-dimensional material and method of manufacturing the same

Semiconductor structure and manufacturing method thereof

Horizontal gate all around and FinFET device isolation

Dual nitride stressor for semiconductor device and method of manufacturing

Method for manufacturing a CMOS device and associated device

FinFET with constrained source-drain epitaxial region

Reverse tone self-aligned contact

Two-dimensional condensation for uniaxially strained semiconductor fins

Nanowire and method of fabricating the same

Silicon IMPATT diode

Silicon germanium alloy fins with reduced defects

Semiconductor device including fin structures and manufacturing method therof

Source/drain structure and manufacturing the same

Semiconductor device and method of forming the same

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

N-type fin field-effect transistor and fabrication method thereof