Application of super lattice films on insulator to lateral bipolar transistors

Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs

Tunneling field effect transistor (TFET) having a semiconductor fin structure

Semiconductor device including Fin-FET and manufacturing method thereof

Semiconductor structure and manufacturing method thereof

Metal gate scheme for device and methods of forming

Body-tied, strained-channel multi-gate device and methods

Staggered-type tunneling field effect transistor

Selective germanium P-contact metalization through trench

FETs and methods of forming FETs

Method of forming performance optimized gate structures by silicidizing lowered source and drain regions

Low defect relaxed SiGe/strained Si structures on implant anneal buffer/strain relaxed buffer layers with epitaxial rare earth oxide interlayers and methods to fabricate same

Low defect relaxed SiGe/strained Si structures on implant anneal buffer/strain relaxed buffer layers with epitaxial rare earth oxide interlayers and methods to fabricate same

Semiconductor devices including fin bodies with varied epitaxial layers

FinFET devices having asymmetrical epitaxially-grown source and drain regions and methods of forming the same

Method and structure for forming dielectric isolated FinFET with improved source/drain epitaxy

Active regions with compatible dielectric layers

Semiconductor device having asymmetrical source/drain

Semiconductor device having contact plugs and method of forming the same

Semiconductor device

Structures and devices including germanium-tin films and methods of forming same

Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer

Epitaxial source/drain differential spacers

Semiconductor device and fabrication method thereof

Semiconductor devices having source/drain regions with strain-inducing layers and methods of manufacturing such semiconductor devices

SHAPED CAVITY FOR SIGE FILLING MATERIAL

Shaped cavity for SiGe filling material

Semiconductor device including Fin structures and manufacturing method thereof

Semiconductor device and method for fabricating the same

FinFET conformal junction and high epi surface dopant concentration method and device

Semiconductor devices including contact structures that partially overlap silicide layers

Method to induce strain in finFET channels from an adjacent region

Semiconductor devices and methods of fabricating the same

Semiconductor-on-insulator (SOI) lateral heterojunction bipolar transistor having an epitaxially grown base

Semiconductor-on-insulator (SOI) lateral heterojunction bipolar transistor having an epitaxially grown base

Semiconductor device having fin structure that includes dummy fins

Semiconductor device including field effect transistors

FinFET with high mobility and strain channel

FinFETs having strained channels, and methods of fabricating finFETs having strained channels

Vertical tunneling FinFET

Structure and method for a field effect transistor

Structure and formation method of semiconductor device structure

FinFET device having a high germanium content fin structure and method of making same

Bi-axial tensile strained GE channel for CMOS

Semiconductor devices

FinFET device with vertical silicide on recessed source/drain epitaxy regions

Spasers to speed up CMOS processors

FinFETs with strained well regions

Method for making a semiconductor device with sidewal spacers for confinig epitaxial growth

Bulk finFET with partial dielectric isolation featuring a punch-through stopping layer under the oxide

Epitaxial channel with a counter-halo implant to improve analog gain

Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction and semiconductor device having reduced junction leakage

NPN heterojunction bipolar transistor in CMOS flow

Formation of FinFET junction

Semiconductor device including active fin

Semiconductor device structure with raised source/drain having cap element

Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction

Method for fabricating semiconductor device having fin structure that includes dummy fins

Heterogeneous pocket for tunneling field effect transistors (TFETs)

Asymmetric FET

Semiconductor device formed with nanowire

FinFET including tunable fin height and tunable fin width ratio

Semiconductor devices having fin active regions

Method of forming a semiconductor structure

Method of making a CMOS semiconductor device using a stressed silicon-on-insulator (SOI) wafer

Fully depleted device with buried insulating layer in channel region

Method for fabricating semiconductor structures including fin structures with different strain states, and related semiconductor structures

Method for manufacturing a transistor

Semiconductor devices having 3D channels, and methods of fabricating semiconductor devices having 3D channels

Double aspect ratio trapping

Super junction semiconductor device having columnar super junction regions extending into a drift layer

Methods, apparatus and system for providing source-drain epitaxy layer with lateral over-growth suppression

COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (CMOS) TRANSISTOR AND TUNNEL FIELD-EFFECT TRANSISTOR (TFET) ON A SINGLE SUBSTRATE

Integrate circuit with nanowires

Double aspect ratio trapping

Epitaxial growth of crystalline material

Embedded source/drain structure for tall finFET and method of formation

Fin field-effect transistor

Semiconductor device with low band-to-band tunneling

FinFETs having step sided contact plugs and methods of manufacturing the same

FETs and methods for forming the same

Contact structure of semiconductor device

Modulating germanium percentage in MOS devices

V-shaped SiGe recess volume trim for improved device performance and layout dependence

LDD-free semiconductor structure and manufacturing method of the same

Methods of modulating strain in PFET and NFET FinFET semiconductor devices

Metal gate stack having TaAlCN layer

COMPOUND SEMICONDUCTOR STRUCTURE

METHODS FOR FABRICATING SEMICONDUCTOR STRUCTURE WITH CONDENSED SILICON GERMANIUM LAYER

MODIFIED-RESIST STRIPPER, METHOD FOR STRIPPING MODIFIED RESIST USING SAME, AND METHOD FOR MANUFACTURING SEMICONDUCTOR-SUBSTRATE PRODUCT

Transistors, methods of forming transistors and display devices having transistors

Semiconductor devices

Semiconductor devices and fabrication method thereof

Field-effect transistor with aggressively strained fins

FinFETs and the methods for forming the same

CHANNEL LAST REPLACEMENT FLOW FOR BULK FINFETS

FORMING STRAINED FINS OF DIFFERENT MATERIALS ON A SUBSTRATE

Method of forming MOSFET structure

Method of co-integration of strained silicon and strained germanium in semiconductor devices including fin structures

Compound semiconductor transistor with gate overvoltage protection

Replacement metal gates to enhance transistor strain

Stacked Gate-All-Around FinFET and method forming the same

Epitaxial wafer and method of manufacturing the same

Reacted conductive gate electrodes and methods of making the same

Structure and method for transistors with line end extension

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE WITH RECESS, EPITAXIAL GROWTH AND DIFFUSION

Semiconductor devices with shaped cavities for embedding germanium material and manufacturing processes thereof

Transistor structure with variable clad/core dimension for stress and bandgap

FINFETs with wrap-around silicide and method forming the same

Structure and formation method of FinFET device

Bipolar junction transistor (BJT) base conductor pullback

CMOS FinFET device having strained SiGe fins and a strained Si cladding layer on the NMOS channel

Semiconductor device including fin structures and manufacturing method thereof

Transistor device with gate control layer undercutting the gate dielectric

Semiconductor device and method of forming the same

Semiconductor structure and manufacturing method thereof

Deep gate-all-around semiconductor device having germanium or group III-V active layer

Method of preventing epitaxy creeping under the spacer

High selectivity nitride removal process based on selective polymer deposition

Semiconductor devices with shaped portions of elevated source/drain regions

Selector device for a non-volatile memory cell

Formation of strained fins in a finFET device

Dual isolation on SSOI wafer

CMOS structure on SSOI wafer

Integrated circuit device and method of manufacturing the same

Heterogeneous multicore processor with graphene-based transistors

Semiconductor device

Semiconductor device structure and manufacturing method thereof

Method and device for high k metal gate transistors

Semiconductor device

Method for forming metal oxide semiconductor device

Method for fabricating semiconductor device

Methods of forming fin isolation regions under tensile-strained fins on FinFET semiconductor devices

Methods of forming NMOS and PMOS FinFET devices and the resulting product

Semiconductor device including fin structure with two channel layers and manufacturing method thereof

Integration of strained silicon germanium PFET device and silicon NFET device for FINFET structures

SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME

Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regions

Anchored stress-generating active semiconductor regions for semiconductor-on-insulator FinFET

Integration of strained silicon germanium PFET device and silicon NFET device for finFET structures

Methods for fabricating semiconductor devices having fin-shaped patterns by selectively removing oxidized fin-shaped patterns

Nanowire transistor device and method for manufacturing nanowire transistor device

Defect reduction using aspect ratio trapping

Semiconductor device and method for fabricating the same

Nonplanar device and strain-generating channel dielectric

FinFET with dielectric isolated channel

Method to form localized relaxed substrate by using condensation

FinFET with multilayer fins for multi-value logic (MVL) applications and method of forming

METHODS FOR PREVENTING OXIDATION DAMAGE DURING FINFET FABRICATION

Semiconductor device and manufacturing method thereof

Semiconductor device including fin structures and manufacturing method thereof

Semiconductor device and method for fabricating the same

Method for semiconductor device fabrication

Semiconductor devices, FinFET devices, and manufacturing methods thereof

Non-silicon device heterolayers on patterned silicon substrate for CMOS by combination of selective and conformal epitaxy

Method and structure for finFET devices

Structure and formation method of finFET device

High efficiency FinFET diode

Semiconductor device and method of manufacturing the same

Self-aligned contact process enabled by low temperature

Methods of forming dislocation enhanced strain in NMOS structures

Method of making a finFET, and finFET formed by the method

Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation

Formation of dislocations in source and drain regions of FinFET devices

DEVICES WITH FULLY AND PARTIALLY SILICIDED GATE STRUCTURES IN GATE FIRST CMOS TECHNOLOGIES

Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process

MOSFET structure and manufacturing method thereof

Method and device for a FinFET

Method to controllably etch silicon recess for ultra shallow junctions

Semiconductor device having embedded strain-inducing pattern and method of forming the same

Method to controllably etch silicon recess for ultra shallow junctions

FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth

Method for fabricating transistor with thinned channel

Tunnel field effect transistors having low turn-on voltage

Tunnelling field effect transistor

Performance optimized gate structures having memory device and logic device, the memory device with silicided source/drain regions that are raised with respect to silicided source/drain regions of the logic device

Structure and method for advanced bulk fin isolation

Structure and method for advanced bulk fin isolation

Field-effect transistor and semiconductor device

Strain compensation in transistors

Surface tension modification using silane with hydrophobic functional group for thin film deposition

Non-Planar Semiconductor Devices having Multi-Layered Compliant Substrates

Hetero-channel FinFET

Vertical gate all-around transistor

Silicon germanium-on-insulator FinFET

Transistor and method of making

Surface passivation for germanium-based semiconductor structure

Vertical transistor devices for embedded memory and logic technologies

Bipolar transistor structure and a method of manufacturing a bipolar transistor structure

V-shaped epitaxially formed semiconductor layer

Semiconductor device and manufacturing method thereof

FinFET contact structure and method for forming the same

Semiconductor device structure and method for forming the same

Structure and method for semiconductor device

Semiconductor device

Semiconductor devices with an etch stop layer on gate end-portions located above an isolation region

Method for manufacturing semiconductor device

Methods of forming low band gap source and drain structures in microelectronic devices

Semiconductor devices and methods for fabricating the same

Method for forming semiconductor structure with etched fin structure

Finfet based ZRAM with convex channel region

Methods and structures to prevent sidewall defects during selective epitaxy

FinFET with epitaxial source and drain regions and dielectric isolated channel region

Method to induce strain in 3-D microfabricated structures

Semiconductor structure and method for manufacturing the same

Techniques for forming non-planar germanium quantum well devices

SiGe finFET with improved junction doping control

Method to reduce etch variation using ion implantation

Active regions with compatible dielectric layers

FinFET with a silicon germanium alloy channel and method of fabrication thereof

MOSFET structure and manufacturing method thereof

Methods of Forming Field Effect Transistors Having Silicon-Germanium Source/Drain Regions Therein

Biosensor based on heterojunction bipolar transistor

BIOSENSOR BASED ON HETEROJUNCTION BIPOLAR TRANSISTOR

Semiconductor devices including an etch stop pattern and a sacrificial pattern with coplanar upper surfaces and a gate and a gap fill pattern with coplanar upper surfaces

Semiconductor device having stressor and method of forming the same

Nitride layer protection between PFET source/drain regions and dummy gate during source/drain etch

Vertical nanowire transistor with axially engineered semiconductor and gate metallization

FINFET semiconductor device and fabrication method

Gate all around device structure and Fin field effect transistor (FinFET) device structure

Semiconductor device and method for manufacturing the same

High resistance layer for III-V channel deposited on group IV substrates for MOS transistors

Semiconductor devices and methods for manufacturing the same

Semiconductor devices including a dummy gate structure on a fin

Semiconductor device having a substrate including a first active region and a second active region

Forming self-aligned NiSi placement with improved performance and yield

Passivated and faceted fin field effect transistor

Transistor strain-inducing scheme

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

Semiconductor device and fabricating method thereof

CMOS devices having dual high-mobility channels

Semiconductor component including a short-circuit structure

Transistors incorporating metal quantum dots into doped source and drain regions

Reducing direct source-to-drain tunneling in field effect transistors with low effective mass channels

Facet-free strained silicon transistor

Enhanced method of introducing a stress in a transistor channel by means of sacrificial sources/drain regions and gate replacement

Gate spacers and methods of forming

Semiconductor devices including a stressor in a recess and methods of forming the same

High-voltage FinFET device having LDMOS structure and method for manufacturing the same

Semiconductor devices including field effect transistors and methods of forming the same

Diamond Like Carbon (DLC) in a Semiconductor Stack as a Selector for Non-Volatile Memory Application

Fin shape structure

Method of making semiconductor structure having contact plug

Semiconductor device having tipless epitaxial source/drain regions

Semiconductor transistor having a stressed channel

Reduced scale resonant tunneling field effect transistor

Structure and method to make strained FinFET with improved junction capacitance and low leakage

Semiconductor device having a metal gate

Semiconductor structure and device formed using selective epitaxial process

Semiconductor device

FinFET device including a uniform silicon alloy fin

Semiconductor device and method for fabricating the same

FinFETs with source/drain cladding

Transistor and fabrication method thereof

Transistor structures and fabrication methods thereof

Semiconductor device structure and method for forming the same

High dose implantation for ultrathin semiconductor-on-insulator substrates

Method to form strained channel in thin box SOI structures by elastic strain relaxation of the substrate

Multi-gate FETs having corrugated semiconductor stacks and method of forming the same

Floating body memory with asymmetric channel

Self-aligned contact metallization for reduced contact resistance

Method of forming source/drain contact

Fin field effect transistor (FinFET) device and method for forming the same

Fin field effect transistor (FinFET) device and method for forming the same

High mobility PMOS and NMOS devices having Si—Ge quantum wells

Semiconductor devices and methods of forming the same

Contact resistance reduction technique

Threshold adjustment for quantum dot array devices with metal source and drain

Multi-channel gate-all-around FET

Transistor with performance boost by epitaxial layer

High-integration semiconductor device and method for fabricating the same

Method for making high voltage integrated circuit devices in a fin-type process and resulting devices

Fin field effect transistor (FinFET) device and method for forming the same

Semiconductor structure with self-aligned wells and multiple channel materials

MOSFETs with channels on nothing and methods for forming the same

Methods for producing low oxygen silicon ingots

Memory devices, methods of manufacturing the same, and methods of accessing the same

Body-tied, strained-channel multi-gate device and methods of manufacturing same

Methods of forming semiconductor devices including conductive contacts on source/drains

Semiconductor device and method for fabricating the same

Method of making a semiconductor device using a dummy gate

Fin-like field effect transistor (FinFET) device and method of manufacturing same

FETs and methods of forming FETs

Tunneling field effect transistor and methods of making such a transistor

Embedded shape sige for strained channel transistors

Gate structure having designed profile and method for forming the same

OPC enlarged dummy electrode to eliminate ski slope at eSiGe

Vertical semiconductor devices including superlattice punch through stop layer and related methods

Three dimensional NAND device with silicon germanium heterostructure channel

FinFET device having a material formed on reduced source/drain region and method of forming the same

Etching method for forming grooves in Si-substrate and fin field-effect transistor

FinFET LDMOS device and manufacturing methods

Integrated circuit structure with substrate isolation and un-doped channel

Semiconductor structures and fabrication method thereof

Method for creating self-aligned transistor contacts

Double aspect ratio trapping

Semiconductor device and method for fabricating the same

Semiconductor device and method of fabricating the same

Semiconductor devices including a stressor in a recess and methods of forming the same

Method for fabricating semiconductor structures including fin structures with different strain states, and related semiconductor structures