MOS device with island region

Method of making a graphene base transistor with reduced collector area

Semiconductor devices

Transistor device and fabrication method

Method and apparatus for source-drain junction formation in a FinFET with in-situ doping

Semiconductor device and method of fabricating the same

Fin-type graphene device

Method and structure for FinFET device

Methods for high-k metal gate CMOS with SiC and SiGe source/drain regions

Semiconductor structure with strained source and drain structures and method for forming the same

Semiconductor device structure with gate spacer having protruding bottom portion and method for forming the same

Isolation structure of semiconductor device

Structure and method for SRAM FinfET device

Device having EPI film in substrate trench

Semiconductor devices including a stressor in a recess and methods of forming the same

Enhanced dislocation stress transistor

Non-planar gate all-around device and method of fabrication thereof

Semiconductor device and method for fabricating the same

Semiconductor structure and manufacturing method of the same

Method to co-integrate oppositely strained semiconductor devices on a same substrate

Semiconductor structure and fabricating method thereof

Performance enhancement in transistors by providing an embedded strain-inducing semiconductor material on the basis of a seed layer

Apparatus and method for forming semiconductor contacts

Semiconductor device structure

Leakage current suppression methods and related structures

NATIVE PMOS DEVICE WITH LOW THRESHOLD VOLTAGE AND HIGH DRIVE CURRENT AND METHOD OF FABRICATING THE SAME

High mobility strained channels for fin-based transistors

Method for the formation of a FinFET device with epitaxially grown source-drain regions having a reduced leakage path

Method of making a semiconductor device using spacers for source/drain confinement

Semiconductor devices including a stressor in a recess and methods of forming the same

FinFET semiconductor device with isolated fins made of alternative channel materials

FinFET with a silicon germanium alloy channel and method of fabrication thereof

Semiconductor device and fabrication method thereof

Method of manufacturing semiconductor devices

Germanium-based quantum well devices

Semiconductor device structure and method for forming the same

Borderless contact formation through metal-recess dual cap integration

Growth of semiconductors on hetero-substrates using graphene as an interfacial layer

Method for forming semiconductor device structure

Substrate of semiconductor device including epitaxial layer and silicon layer having same crystalline orientation

Lateral PiN diodes and schottky diodes

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Fin-like field effect transistor (FinFET) device and method of manufacturing same

Fin field-effect transistors and fabrication methods thereof

Dual channel material for finFET for high performance CMOS

Formation of nickel silicon and nickel germanium structure at staggered times

Nanowire nanoelectromechanical field-effect transistors

Semiconductor device and fabrication method therefor

Metal-insensitive epitaxy formation

Integrated circuits with diffusion barrier layers and processes for preparing integrated circuits including diffusion barrier layers

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND A SYSTEM HAVING THE SAME

Finfet including improved epitaxial topology

Two-dimensional condensation for uniaxially strained semiconductor fins

Semiconductor devices and methods of fabricating the same

Semiconductor devices with germanium-rich active layers and doped transition layers

Semiconductor structure and manufacturing method thereof

Structure and method for FinFET device

Semiconductor device and fabrication method thereof

Tunneling field effect transistor having a three-side source and fabrication method thereof

Semiconductor device structure and method for forming the same

Semiconductor devices including an isolation layer on a fin and methods of forming semiconductor devices including an isolation layer on a fin

FinFET with constrained source-drain epitaxial region

Raised metal semiconductor alloy for self-aligned middle-of-line contact

Multi-gate devices with replaced-channels and methods for forming the same

FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth

Methods of forming stressed channel regions for a FinFET semiconductor device and the resulting device

Strained channel of gate-all-around transistor

Transistor design

Semiconductor channel-stop layer and method of manufacturing the same

Semiconductor device having silicon-germanium source/drain regions with varying germanium concentrations

Methods of fabricating a semiconductor device

Method of making a strained structure of a semiconductor device

Silicide formation due to improved SiGe faceting

Source/drain structures and methods of forming same

Semiconductor devices having source/drain regions with strain-inducing layers and methods of manufacturing such semiconductor devices

Nanowire field effect transistor device having a replacement gate

FinFET device with abrupt junctions

Method for forming a germanium channel layer for an NMOS transistor device, NMOS transistor device and CMOS device

Method for providing an NMOS device and a PMOS device on a silicon substrate and silicon substrate comprising an NMOS device and a PMOS device

FinFET device with dual-strained channels and method for manufacturing thereof

MOS devices with thinned gate spacers and methods of thinning the gate spacers

Semiconductor device and fabrication method thereof

Semiconductor device having insulating pattern and method of forming the same

Non-planar quantum well device having interfacial layer and method of forming same

Methods of manufacturing semiconductor devices

Semiconductor device and method for manufacturing the same

Fin-based semiconductor device including a metal gate diffusion break structure with a conformal dielectric layer

FinFET source-drain merged by silicide-based material

Methods of manufacturing semiconductor devices by forming source/drain regions before gate electrode separation

Semiconductor structure and manufacturing method thereof

Methods of forming low defect replacement fins for a FinFET semiconductor device and the resulting devices

FinFET with constrained source-drain epitaxial region

Field effect transistor and method of fabricating the same

Semiconductor structure and manufacturing method thereof

Processes for fabricating FinFET structures with semiconductor compound portions formed in cavities and extending over sidewall spacers

Fin spacer protected source and drain regions in FinFETs

FinFETs with necking in the fins

Stain compensation in transistors

Method for fabricating a strained structure and structure formed

Semiconductor devices including source/drain regions having multiple epitaxial patterns

FinFETs with strained well regions

Strained source and drain (SSD) structure and method for forming the same

Semiconductor devices and fabrication method thereof

Method for producing a microelectronic device

Junction butting structure using nonuniform trench shape

Fin-last FinFET and methods of forming same

Structure and method for SRAM FinFET device

Method of forming different voltage devices with high-k metal gate

Integrated circuit structure and method with solid phase diffusion

Semiconductor device and manufacturing method thereof

CONSTRAINING EPITAXIAL GROWTH ON FINS OF A FINFET DEVICE

Apparatus and method for multiple gate transistors

Method and structure for protecting gates during epitaxial growth

Multi-channel gate-all-around FET

Three dimensional semiconductor device having lateral channel

Methods and apparatus for training an artificial neural network for use in speech recognition

FinFET and nanowire semiconductor devices with suspended channel regions and gate structures surrounding the suspended channel regions

Device with engineered epitaxial region and methods of making same

Structure and method for integrated circuit

Graphene-metal bonding structure, method of manufacturing the same, and semiconductor device having the graphene-metal bonding structure

SEMICONDUCTOR DEVICE

P-FET with graded silicon-germanium channel

Single-chip field effect transistor (FET) switch with silicon germanium (SiGe) power amplifier and methods of forming

Self-aligned interconnect with protection layer

Source/drain structure of semiconductor device

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Semiconductor liner of semiconductor device

Constrained epitaxial source/drain regions on semiconductor-on-insulator finFET device

Semiconductor arrangements and methods for manufacturing the same

DEVICES AND METHODS OF FORMING BULK FINFETS WITH LATERAL SEG FOR SOURCE AND DRAIN ON DIELECTRICS

Tucked active region without dummy poly for performance boost and variation reduction

Semiconductor structure and fabrication method thereof

Method for making a semiconductor device with sidewall spacers for confining epitaxial growth

Deep gate-all-around semiconductor device having germanium or group III-V active layer

Contact resistance optimization via EPI growth engineering

Semiconductor device having strained fin structure and method of making the same

Transistor with embedded stress-inducing layers

Semiconductor structures and fabrication method thereof

Metal oxide semiconductor having epitaxial source drain regions and a method of manufacturing same using dummy gate process

Methods of increasing silicide to epi contact areas and the resulting devices

Semiconductor devices and methods of fabricating the same

Method for embedded diamond-shaped stress element

Drain extended field effect transistors and methods of formation thereof

Integrated RF front end system

Passivation structure of fin field effect transistor

Method and apparatus of forming an integrated circuit with a strained channel region

Semiconductor device and method for manufacturing the same

Methods of fabricating semiconductor fin structures

Selective germanium P-contact metalization through trench

Semiconductor device

MULTI-HEIGHT MULTI-COMPOSITION SEMICONDUCTOR FINS

Techniques providing metal gate devices with multiple barrier layers

Integrate circuit with nanowires

FinFET and method for manufacturing the same

Fin field effect transistor (finFET) device including a set of merged fins formed adjacent a set of unmerged fins

Semiconductor device structure having multi-layered insulating cap layers over metal gate

Integrated electronic device and method for manufacturing thereof

Structures and formation methods of finFET device

Methods for introducing carbon to a semiconductor structure and structures formed thereby

Semiconductor device and method of manufacturing the same

Semiconductor device and method of manufacturing the same

Methods for forming semiconductor regions in trenches

Methods of forming defect-free SRB onto lattice-mismatched substrates and defect-free fins on insulators

Semiconductor device and manufacturing method therefor

Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction

Forming alternative material fins with reduced defect density by performing an implantation/anneal defect generation process

Structure and method for FinFET device

Structure and method for FinFET device

Self-aligned emitter-base-collector bipolar junction transistors with a single crystal raised extrinsic base

Semiconductor devices utilizing partially doped stressor film portions

Semiconductor device and method of fabricating the same

Structure and method for SRAM FinFET device having an oxide feature

Structure and method for FinFET device

Semiconductor device

Fabricating field effect transistor(s) with stressed channel region(s) and low-resistance source/drain regions

FinFET device with high-k metal gate stack

Semiconductor device having multiple active area layers and its formation thereof

Method to induce strain in finFET channels from an adjacent region

Method of fabricating a MOSFET with an undoped channel

Base profile of self-aligned bipolar transistors for power amplifier applications

Method for manufacturing fin structure

Silicon and silicon germanium nanowire structures

Method to co-integrate oppositely strained semiconductor devices on a same substrate

Three-dimensional semiconductor memory devices including a vertical channel

Method and structure for FinFET device

BiCMOS integration using a shared SiGe layer

Efficient fabrication of BiCMOS devices

Low-cost complementary BiCMOS integration scheme

Dual pocket approach in PFETs with embedded SI-GE source/drain

Semiconductor device and fabrication method thereof

Method of manufacturing MOSFET

Defect-free relaxed covering layer on semiconductor substrate with lattice mismatch

Methods of forming substantially self-aligned isolation regions on FinFET semiconductor devices and the resulting devices

MOS devices with ultra-high dielectric constants and methods of forming the same

Semiconductor device including field effect transistor

Semiconductor devices and methods for manufacturing the same

Method of forming well-controlled extension profile in MOSFET by silicon germanium based sacrificial layer

Transistors having strained channel under gate in a recess

SiGe FinFET with improved junction doping control

Method for manufacturing a transistor device

Semiconductor device and method for manufacturing same

FinFET including tunable fin height and tunable fin width ratio

FinFET semiconductor device having integrated SiGe fin

Self-aligned contact process enabled by low temperature

Semiconductor devices and methods of fabricating the same

Semiconductor device with fin and related methods

Semiconductor structure and method for manufacturing the same

Direct tunnel barrier control gates in a two-dimensional electronic system

Method of making semiconductor device

Constrained epitaxial source/drain regions on semiconductor-on-insulator finFET device

Combination FinFET and methods of forming same

Bottle-neck recess in a semiconductor device

Semiconductor device including at least one type of deep-level dopant

Abrupt source/drain junction formation using a diffusion facilitation layer

Abrupt source/drain junction formation using a diffusion facilitation layer

Semiconductor device and method for fabricating the same

Methods of forming low-defect strain-relaxed layers on lattice-mismatched substrates and related semiconductor structures and devices

Compact memory structure including tunneling diode

Semiconductor device and method of fabricating the same

Recess and epitaxial layer to improve transistor performance

Semiconductor process for modifying shape of recess

FinFET structure and method for fabricating the same

Method of forming semiconductor device having stressor

Heterojunction bipolar transistors with intrinsic interlayers

Integrated circuit having heterostructure FinFET with tunable device parameters and method to fabricate same

Epitaxial channel

Application of super lattice films on insulator to lateral bipolar transistors

Semiconductor devices with core-shell structures

FinFETs with strained well regions

Sandwich epi channel for device enhancement

Conformity control for metal gate stack

N-work function metal with crystal structure

Semiconductor devices and methods for manufacturing the same

SEMICONDUCTOR DEVICE HAVING STRESSOR AND METHOD OF FABRICATING THE SAME

Structure and method to make strained FinFET with improved junction capacitance and low leakage

Methods for forming wrap around contact

Semiconductor integrated circuit with dislocations

Semiconductor structure and manufacturing method thereof

Semiconductor devices and methods of manufacture thereof

Semiconductor device and manufacturing method thereof

FinFETs of different compositions formed on a same substrate

Methods of forming alternative channel materials on a non-planar semiconductor device and the resulting device

Multi-layer strained channel FinFET

Transistor having a heterojunction and manufacturing method thereof

Semiconductor transistor device with dopant profile

Nanoscale structure with epitaxial film having a recessed bottom portion

Blanket EPI super steep retrograde well formation without Si recess

Field-effect semiconductor device

Methods for forming semiconductor device structures

Semiconductor arrangement with stress control and method of making

Integrated circuit devices including FinFETs and methods of forming the same

Reacted conductive gate electrodes and methods of making the same

Ambipolar synaptic devices

Ambipolar synaptic devices

Method for fabricating semiconductor device, and semiconductor device made thereby

Semiconductor device and formation thereof

Semiconductor structures and methods for multi-level band gap energy of nanowire transistors to improve drive current

Fin field effect transistor (FinFET) device and method for forming the same

Semiconductor device and manufacturing method thereof

Gate structure of field effect transistor with footing

Reduced variation MOSFET using a drain-extension-last process

Semiconductor device including groups of stacked nanowires and related methods

Reverse tone self-aligned contact

Ambipolar synaptic devices

Semiconductor substructure having elevated strain material-sidewall interface and method of making the same

Method of fabricating spacers in a strained semiconductor device

Field effect transistor with heterostructure channel

FinFET device with abrupt junctions

Silicon on insulator device with partially recessed gate

Formation of an asymmetric trench in a semiconductor substrate and a bipolar semiconductor device having an asymmetric trench isolation region

Side gate assist in metal gate first process

Integrated circuits with relaxed silicon / germanium fins

Semiconductor device and method for manufacturing the same

Semiconductor structure having contact plug and method of making the same

Modulating germanium percentage in MOS devices

Method of manufacturing a FinFET device using a sacrificial epitaxy region for improved fin merge and FinFET device formed by same

Semiconductor device and method of manufacturing

Strained FinFET and method for manufacturing the same

Semiconductor device including spacers having different dimensions

Source and drain doping profile control employing carbon-doped semiconductor material

Semiconductor devices and methods of manufacturing the same

1T SRAM/DRAM

1T SRAM/DRAM

High dose implantation for ultrathin semiconductor-on-insulator substrates

Method of manufacturing a semiconductor device using source/drain epitaxial overgrowth for forming self-aligned contacts without spacer loss and a semiconductor device formed by same

Semiconductor devices and methods of fabricating the same

Semiconductor device including superlattice SiGe/Si fin structure

Semiconductor device and fabrication method thereof

Tuning strain in semiconductor devices

Graphene heterostructure field effect transistors

Aligned gate-all-around structure

Epitaxial formation of source and drain regions

ULTRATHIN BODY FULLY DEPLETED SILICON-ON-INSULATOR INTEGRATED CIRCUITS AND METHODS FOR FABRICATING SAME

High-K metal gate process for lowering junction leakage and interface traps in NMOS transistor

Semiconductor devices and methods of manufacturing the same

Method of making a CMOS semiconductor device using a stressed silicon-on-insulator (SOI) wafer

Body-tied, strained-channel multi-gate device and methods of manufacturing same

Semiconductor device, related manufacturing method, and related electronic device

Field effect transistor (FET) with self-aligned double gates on bulk silicon substrate, methods of forming, and related design structures

Formation of a high aspect ratio trench in a semiconductor substrate and a bipolar semiconductor device having a high aspect ratio trench isolation region