208414 ⎘
Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor; Types of semiconductor device ; Multistep manufacturing processes therefor; Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices; Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
SEMICONDUCTOR STRUCTURE
#2METHOD AND SYSTEM FOR VERTICAL FETS FABRICATED ON AN ENGINEERED SUBSTRATE
#3NANO TRANSISTORS WITH SOURCE/DRAIN HAVING SIDE CONTACTS TO 2-D MATERIAL
#4SEMICONDUCTOR POWER DEVICE AND METHOD FOR PRODUCING SAME
#5Nano transistors with source/drain having side contacts to 2-D material
#6SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
#7Semiconductor device having a lateral transistor device and an inverter that includes the semiconductor device
#8GaN vertical-channel junction field-effect transistors with regrown p-GaN by metal organic chemical vapor deposition (MOCVD)
#9Method and system for control of sidewall orientation in vertical gallium nitride field effect transistors
#10Semiconductor power device and method for producing same
#11Nano transistors with source/drain having side contacts to 2-D material
#12Vertical tunnel field-effect transistor with u-shaped gate and band aligner
#13GaN vertical-channel junction field-effect transistors with regrown p-GaN by metal organic chemical vapor deposition (MOCVD)
#14Method for manufacturing thin film transistor and thin film transistor
#15Semiconductor device and inverter
#16Semiconductor power device and method for producing same
#17Semiconductor power device and method for producing same
#18Increased source and drain contact edge width in two-dimensional material field effect transistors by directed self-assembly
#19Vertical tunnel field-effect transistor with U-shaped gate and band aligner
#20Gate structure and method for producing same
#21High switching frequency, low loss and small form factor fully integrated power stage
#22Increased source and drain contact edge width in two-dimensional material field effect transistors by directed self-assembly
#23Layered vertical field effect transistor and methods of fabrication
#24LONG CHANNELS FOR TRANSISTORS
#25High switching frequency, low loss and small form factor fully integrated power stage
#26Semiconductor devices with regrown contacts and methods of fabrication
#27Long channels for transistors
#28Semiconductor device and manufacturing method thereof
#29Field-effect transistor
#30Gallium nitride semiconductor structure and process for fabricating thereof
#31Compound semiconductor field effect transistor with self-aligned gate
#32Semiconductor power device and method for producing same
#33Semiconductor device and electrical device
#34Lateral gallium nitride JFET with controlled doping profile
#35Continuous crystalline gallium nitride (GaN) PN structure with no internal regrowth interfaces
#36Method and system for in-situ etch and regrowth in gallium nitride based devices
#37Semiconductor structure having insulator pillars and semiconductor material on substrate
#38Contact structure and extension formation for III-V nFET
#39Vertical semiconductor device and manufacturing method thereof
#40Contact structure and extension formation for III-V nFET
#41INP-based transistor fabrication
#42Process of forming an electronic device including a multiple channel HEMT
#43Semiconductor device and manufacturing method thereof
#44Semiconductor structure having insulator pillars and semiconductor material on substrate
#45Self-aligned source and drain regions for semiconductor devices
#46Methodologies related to structures having HBT and FET
#47Multi-threshold voltage structures with a lanthanum nitride film and methods of formation thereof
#48III-N transistors with enhanced breakdown voltage
#49Semiconductor power device and method for producing same
#50III-N transistors with epitaxial layers providing steep subthreshold swing
#51Self-aligned source and drain regions for semiconductor devices
#52Self-aligned source and drain regions for semiconductor devices
#53Low-stress low-hydrogen LPCVD silicon nitride
#54Lateral/vertical semiconductor device
#55Low resistance contact for semiconductor devices
#56III-V nitride semiconductor device having reduced contact resistance
#57Driver for normally on III-nitride transistors to get normally-off functionality
#58Low resistance contact for semiconductor devices
#59Manufacturing method of semiconductor device and semiconductor device
#60Semiconductor device and manufacturing method thereof
#61Lateral/vertical semiconductor device
#62Semiconductor device including first and second gate insulating films disposed on a semiconductor layer and manufacturing method of the same
#63Tunneling field effect transistor device and related manufacturing method
#64SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
#65Method and system for planar regrowth in GaN electronic devices
#66Self-Aligned III-V MOSFET Fabrication With In-Situ III-V Epitaxy And In-Situ Metal Epitaxy and Contact Formation
#67Edge termination by ion implantation in gallium nitride
#68Vertical gallium nitride JFET with gate and source electrodes on regrown gate
#69Method and system for a GaN vertical JFET utilizing a regrown channel
#70Method and system for a gallium nitride vertical JFET with self-aligned source and gate
#71Semiconductor device and manufacturing method thereof
#72Methods of fabricating semiconductor devices including implanted regions for providing low-resistance contact to buried layers and related devices
#73Reducing wafer distortion through a high CTE layer
#74Nitride electronic device and method for manufacturing the same
#75Method and system for carbon doping control in gallium nitride based devices
#76Semiconductor device and method for fabricating the same
#77Lateral/vertical semiconductor device
#78Method and system for in-situ etch and regrowth in gallium nitride based devices
#79Method and system for gallium nitride electronic devices using engineered substrates
#80Semiconductor apparatus and method for making semiconductor apparatus
#81Method and system for a GAN vertical JFET with self-aligned source metallization
#82Method and system for planar regrowth in GAN electronic devices
#83Method and system for a GaN vertical JFET with self-aligned source and gate
#84Vertical GaN JFET with gate source electrodes on regrown gate
#85Method and system for carbon doping control in gallium nitride based devices
#86Edge termination by ion implantation in GaN
#87Method and system for local control of defect density in gallium nitride based electronics
#88Vertical field effect transistor on oxide semiconductor substrate
#89InP-based transistor fabrication
#90Method and system for a GaN vertical JFET utilizing a regrown channel
#91Method and system for a GAN vertical JFET utilizing a regrown gate
#92Nitride electronic device and method for manufacturing the same
#93SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF
#94Method of manufacturing semiconductor device using Resolution Enhanced Lithography Assisted Chemical Shrinkage (RELACS)
#95Self-aligned III-V MOSFET fabrication with in-situ III-V epitaxy and in-situ metal epitaxy and contact formation
#96Method to reduce contact resistance of N-channel transistors by using a III-V semiconductor interlayer in source and drain
#97Devices and methodologies related to structures having HBT and FET
#98Reducing wafer distortion through a high CTE layer
#99Method for making nanowire element
#100PROCESS FOR FORMING LOW DEFECT DENSITY HETEROJUNCTIONS
#101PROCESS FOR FORMING LOW DEFECT DENSITY HETEROJUNCTIONS
#102Nitride semiconductor device and method for producing nitride semiconductor device
#103InP-based transistor fabrication
#104Semiconductor devices including implanted regions for providing low-resistance contact to buried layers and related devices
#105Process for forming low defect density heterojunctions
#106Vertical junction field effect transistors, and methods of producing the vertical junction field effect transistors
#107Vertical junction field effect transistors, and methods of producing the vertical junction field effect transistors
#108Integrated circuit structure incorporating a stacked pair of field effect transistors and a buried interconnect and method