242015 ⎘
Semiconductor device manufacturing: process Dummy metallization
Method for fabricating transistor with thinned channel
#2Semiconductor device
#3Method for fabricating transistor with thinned channel
#4Semiconductor device
#5Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
#6Method for fabricating transistor with thinned channel
#7Method of manufacturing a semiconductor device
#8Semiconductor device, method for manufacturing the same, method for generating mask data, mask and computer readable recording medium
#9Method for fabricating transistor with thinned channel
#10Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
#11Semiconductor device, method for manufacturing the same, method for generating mask data, mask and computer readable recording medium
#12Method of manufacturing a semiconductor device
#13Method of manufacturing a semiconductor device
#14Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
#15Semiconductor device, method for manufacturing the same, method for generating mask data, mask and computer readable recording medium
#16PMOS transistors and fabrication method
#17Semiconductor device having ring-shaped gate electrode, design apparatus, and program
#18Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
#19Semiconductor device and method of manufacturing the same
#20Semiconductor device, method for manufacturing the same, method for generating mask data, mask and computer readable recording medium
#21Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
#22METHOD FOR SELF-ALIGNING A STOP LAYER TO A REPLACEMENT GATE FOR SELF-ALIGNED CONTACT INTEGRATION
#23Semiconductor memory device and method of fabricating the same
#24SEMICONDUCTOR DEVICE AND METHOD OF FORMING GATE AND METAL LINE THEREOF
#25Semiconductor device and method of manufacturing the same
#26Semiconductor device, method for manufacturing the same, method for generating mask data, mask and computer readable recording medium
#27Chemical mechanical polishing (CMP) method for gate last process
#28Semiconductor device having dummy pattern and the method for fabricating the same
#29Semiconductor device having ring-shaped gate electrode, design apparatus, and program
#30Semiconductor memory device and method of fabricating the same
#31Carrier mobility enhanced channel devices and method of manufacture
#32FABRICATION OF CHANNEL WRAPAROUND GATE STRUCTURE FOR FIELD-EFFECT TRANSISTOR
#33Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
#34Method for fabricating transistor with thinned channel
#35Method for self-aligning a stop layer to a replacement gate for self-aligned contact integration
#36METAL GATE TRANSISTOR AND METHOD FOR FABRICATING THE SAME
#37Stacked structures and methods of fabricating stacked structures
#38Methods of manufacturing metal-silicide features
#39Semiconductor device, method for manufacturing the same, method for generating mask data, mask and computer readable recording medium
#40Methods of manufacturing metal-silicide features
#41Method of manufacturing semiconductor device that uses both a normal photomask and a phase shift mask for defining interconnect patterns
#42Chemical mechanical polishing (CMP) method for gate last process
#43Metal gate transistor and method for fabricating the same
#44Downsize polysilicon height for polysilicon resistor integration of replacement gate process
#45High-k/metal gate MOSFET with reduced parasitic capacitance
#46Carrier mobility enhanced channel devices and method of manufacture
#47CMOS DEVICE WITH METAL AND SILICIDE GATE ELECTRODES AND A METHOD FOR MAKING IT
#48Virtual ground memory array and method therefor
#49METHOD OF FORMING A NONPLANAR TRANSISTOR WITH SIDEWALL SPACERS
#50Semiconductor device, method for manufacturing semiconductor device, and method for manufacturing semiconductor memory device
#51Structures and methods for reduction of parasitic capacitances in semiconductor integrated circuits
#52Semiconductor device including thermally dissipating dummy pads
#53Method of forming CMOS device having gate insulation layers of different type and thickness
#54Tunneling effect transistor with self-aligned gate
#55Integrated circuit system with dummy region
#56High-k/metal gate MOSFET with reduced parasitic capacitance
#57Semiconductor memory device and method of fabricating the same
#58Structure for charge dissipation during fabrication of integrated circuits and isolation thereof
#59Semiconductor device and method of forming gate and metal line thereof with dummy pattern and auxiliary pattern
#60Method of manufacturing semiconductor device that uses both a normal photomask and a phase shift mask for defining interconnect patterns
#61Process for wafer bonding
#62Semiconductor device having dummy pattern and the method for fabricating the same
#63Metal gate transistors with raised source and drain regions formed on heavily doped substrate
#64CMOS device with metal and silicide gate electrodes and a method for making it
#65Stacked structures and methods of fabricating stacked structures
#66Nonplanar transistors with metal gate electrodes
#67Semiconductor device, method for manufacturing the same, method for generating mask data, mask and computer readable recording medium
#68Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
#69Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
#70Methods of manufacturing metal-silicide features
#71Integrated circuit system with dummy region
#72Method of manufacturing semiconductor device using dummy gate wiring layer
#73Method of forming a semiconductor device having dummy features
#74Semiconductor device with a dummy gate and a method of manufacturing a semiconductor device with a dummy gate
#75Method for manufacturing an SOI substrate
#76Semiconductor device having first and second dummy wirings varying in sizes/coverage ratios around a plug connecting part
#77Etch stop and hard mask film property matching to enable improved replacement metal gate process
#78Metal interconnection lines of semiconductor devices and methods of forming the same
#79Self aligned metal gates on high-K dielectrics
#80Self aligned metal gates on high-k dielectrics
#81Single damascene with disposable stencil and method therefore
#82Method and structure for charge dissipation during fabrication of integrated circuits and isolation thereof
#83Metal-substituted transistor gates
#84Metal-substituted transistor gates
#85Self aligned metal gates on high-k dielectrics
#86Metal-substituted transistor gates
#87Method for fabricating transistor with thinned channel
#88Bow control in an electronic package
#89Dual-bit non-volatile memory cell and method of making the same
#90Apparatus for wafer patterning to reduce edge exclusion zone
#91Method of manufacturing a capacitor and a metal gate on a semiconductor device
#92Ultrathin SOI transistor and method of making the same
#93Dummy patterns in integrated circuit fabrication
#94Floating gate memory device and method of manufacturing the same
#95Method of forming a metal oxide dielectric
#96Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material
#97Method of wafer patterning for reducing edge exclusion zone
#98Electronic device including an array and process for forming the same
#99Virtual ground memory array and method therefor
#100Nonplanar transistors with metal gate electrodes
#101Fabrication of channel wraparound gate structure for field-effect transistor
#102Metal gate transistors with epitaxial source and drain regions
#103Method for making a semiconductor device that includes a metal gate electrode
#104Dual-bit non-volatile memory cell and method of making the same
#105Method and apparatus for simulating standard test wafers
#106Integrating n-type and p-type metal gate transistors
#107Methods for integrating replacement metal gate structures
#108Methods of manufacturing metal-silicide features
#109Semiconductor device structure with adhesion-enhanced semiconductor die
#110Method for fabricating flash memory device
#111Three-dimensional structure element and method of manufacturing the element, optical switch, and micro device
#112Method to make corner cross-grid structures in copper metallization
#113Pattern forming method and semiconductor device manufactured by using said pattern forming method
#114CMOS device with metal and silicide gate electrodes and a method for making it
#115Methods for integrating replacement metal gate structures
#116Metal interconnection lines of semiconductor devices and methods of forming the same
#117Semiconductor device having dummy wiring layers and a method for manufacturing the same
#118Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
#119integrating n-type and P-type metal gate transistors
#120Via array monitor and method of monitoring induced electrical charging
#121Bow control in an electronic package
#122Adhesion enhanced semiconductor die for mold compound packaging