Los Altos, California
United States
33
2026-03-19
The entities that hold a legal rights for patent applications filed by inventor Ware Frederick A.:
Frederick A. Ware from Los Altos, US has applied for patents for these inventions. The list has both pending applications and granted patents:
MEMORY CONTROLLER PARTITIONING FOR HYBRID MEMORY SYSTEM
#2 | 2024-12-05MEMORY CONTROLLER PARTITIONING FOR HYBRID MEMORY SYSTEM
#3 | 2022-03-03Memory controller partitioning for hybrid memory system
#4 | 2015-04-16Load reduced memory module
#5 | 2012-11-15Memory controller with selective data transmission delay
#6 | 2012-08-23Memory controller
#7 | 2012-07-26DYNAMIC PROTOCOL FOR COMMUNICATING COMMAND AND ADDRESS INFORMATION
#8 | 2012-02-16Asynchronous pipelined memory access
#9 | 2011-07-21Method and apparatus for simultaneous bidirectional signaling in a bus topology
#10 | 2011-03-03Control component for controlling a delay interval within a memory component
#11 | 2010-03-11Upgradable system with reconfigurable interconnect
#12 | 2009-10-27Upgradable memory system with reconfigurable interconnect
#13 | 2009-08-27Asynchronous, high-bandwidth memory component using calibrated timing elements
#14 | 2009-05-28Method and apparatus for signaling between devices of a memory system
#15 | 2009-03-05Memory module with termination component
#16 | 2009-01-27Method and apparatus for signaling between devices of a memory system
#17 | 2008-06-19Asynchronous, high-bandwidth memory component using calibrated timing elements
#18 | 2007-11-01Memory controller device having timing offset capability
#19 | 2007-10-25Clocked memory system with termination component
#20 | 2007-05-29Method and apparatus for coordinating memory operations among diversely-located memory components
#21 | 2006-10-19Upgradable memory system with reconfigurable interconnect
#22 | 2006-06-15Method, system and memory controller utilizing adjustable read data delay settings
#23 | 2006-04-13Method and apparatus for simultaneous bidirectional signaling in a bus topology
#24 | 2006-04-13Memory module with termination component
#25 | 2006-03-30Method, system and memory controller utilizing adjustable write data delay settings
#26 | 2006-02-23Memory module with termination component
#27 | 2006-01-12Memory module with termination component
#28 | 2005-12-13Method and apparatus for simultaneous bidirectional signaling in a bus topology
#29 | 2005-10-27Asynchronous, high-bandwidth memory component using calibrated timing elements
#30 | 2005-10-20System for a memory device having a power down mode and method
#31 | 2005-08-23Asynchronous, high-bandwidth memory component using calibrated timing elements
#32 | 2005-08-04Memory device with clock multiplier circuit
#33 | 2005-04-21Granularity memory column access
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