RAMBUS INC.

Clock synchronization in a memory system

Partial-rate transfer mode for fixed-clock-rate interface

Reconfigurable memory controller

Memory system components that support error detection and correction

Selectable-tap equalizer

Signal lines with internal and external termination

Protocol including a command-specified timing reference signal

Testing fuse configurations in semiconductor devices

Atomic-operation coalescing technique in multi-chip systems

Memory interface with reduced read-write turnaround delay

Integrated circuit testing module including signal shaping interface

Code-assisted error-detection technique

Active calibration for high-speed memory devices

Mesochronous signaling system with multiple power modes

Clock-forwarding low-power signaling system

Clock generator circuits with non-volatile memory for storing and/or feedback-controlling phase and frequency

Memory controllers, systems, and methods supporting multiple request modes

Method and apparatus for calibrating write timing in a memory system

Bimodal memory controller

Processor-memory unit for use in system-in-package and system-in-module devices

Locked loop circuit with clock hold function

Signal lines with internal and external termination

Request-command encoding for reduced-data-rate testing

Reducing power-supply-induced jitter in a clock-distribution circuit

Systems and methods for serial cancellation

Methods for estimation and interference cancellation for signal processing

Error detection and offset cancellation during multi-wire communication

Iterative interference canceler for wireless multiple-access systems with multiple receive antennas

Method and apparatus for power sequence timing to mitigate supply resonance in power distribution network

Scalable unified memory architecture

Method and system for balancing receive-side supply load

Encoding data with minimum hamming weight variation

Advanced signal processors for interference cancellation in baseband receivers

Partial response receiver and related method

Programmable memory repair scheme

Apparatus and method for reducing pixel operational voltage in MEMS-based optical displays

Piecewise erasure of flash memory

Advanced signal processors for interference cancellation in baseband receivers

Method and apparatus for selectively applying interference cancellation in spread spectrum systems

Data processing architectures for packet handling wherein batches of data packets of unpredictable size are distributed across processing elements arranged in a SIMD array operable to process different respective packet protocols at once while executing a single common instruction stream

Driver calibration methods and circuits

High-speed source-synchronous signaling

Asymmetric communication on shared links

Edge-based loss-of-signal detection

Simple matrix addressing in a display

Method and apparatus for determining a calibration signal

Encoding and decoding techniques with improved timing margin

Receiver with enhanced clock and data recovery

Encoding and decoding techniques for bandwidth-efficient communication

Memory controllers, methods, and systems supporting multiple memory modes

Technique for determining an angle of arrival in a communication system

Calibration methods and circuits to calibrate drive current and termination impedance

Method and apparatus for evaluating and optimizing a signaling system

Antenna array with flexible interconnect for a mobile wireless device

Configurable on-die termination

Simplified receiver for use in multi-wire communication

Delay lock loop delay adjusting method and apparatus

Variable-width memory

Edge-based sampler offset correction

Techniques for multi-wire encoding with an embedded clock

Adaptive equalization using correlation of edge samples with data patterns

Voltage-stepped low-power memory device

Generating interface adjustment signals in a device-to-device interconnection system

Communication using continuous-phase modulated signals

Reference voltage and impedance calibration in a multi-mode interface

Transforming variable domains for linear circuit analysis

Clock synchronization in a memory system

Multi-antenna transmitter for multi-tone signaling

Clock-data recovery (“CDR”) circuit, apparatus and method for variable frequency data

Multi-antenna beam-forming system for transmitting constant envelope signals decomposed from a variable envelope signal

Single-clock, strobeless signaling system

Memory system topologies including a buffer device and an integrated circuit memory device

Methods and systems for transmitting data by modulating transmitter filter coefficients

Receiver with clock recovery circuit and adaptive sample and equalizer timing

Bi-directional interface circuit having a switchable current-source bias

Adjusting clock error across a circuit interface

Multiphase receiver with equalization

Memory system and device with serialized data transfer

Reference clock and command word alignment

System including hierarchical memory modules having different types of integrated circuit memory devices

Partial response decision-feedback equalization with adaptation based on edge samples

Adjustable width strobe interface