Mark T. RAMSBEY

Memory first process flow and device

Charge trapping split gate device and method of fabricating same

Memory device having programmable impedance elements with a common conductor formed below bit lines

Gate Formation Memory by Planarization

Gate formation memory by planarization

Charge trapping split gate device and method of fabricating same

Memory manufacturing process with bitline isolation

Memory device having trapezoidal bitlines and method of fabricating same

Buried silicide local interconnect with sidewall spacers and method for making the same

Buried silicide local interconnect with sidewall spacers and method for making the same

Anti-reflective interpoly dielectric

Method for forming bit lines for semiconductor devices

Buried silicide local interconnect with sidewall spacers and method for making the same

Nitridation of gate oxide by laser processing

Memory cell having combination raised source and drain and method of fabricating same

Method for forming bit lines for semiconductor devices

Recessed channel with separated ONO memory device

Interface layer between dual polycrystalline silicon layers

Bit line implant

Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact resistance in multi-bit memory devices

Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact resistance in multi bit memory devices

Integrated ONO processing for semiconductor devices using in-situ steam generation (ISSG) process

Semiconductor device and method of fabricating the same

Memory device having trapezoidal bitlines and method of fabricating same

Recessed channel with separated ONO memory device

Memory wordline spacer

UV-blocking layer for reducing UV-induced charging of SONOS dual-bit flash memory devices in BEOL processing

Disposable hard mask for memory bitline scaling

Dual spacer process for non-volatile memory devices

Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same

Laser thermal annealing methods for flash memory devices

Memory cell structure having nitride layer with reduced charge loss and method for fabricating same

Memory device having silicided bitlines and method of forming the same

Flash NVROM devices with UV charge immunity

Hard mask spacer for sublithographic bitline

Bitline hard mask spacer flow for memory cell scaling

Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell

Memory device having high work function gate and method of erasing same

ESD implant following spacer deposition

Method of manufacturing a semiconductor memory with deuterated materials

Implant damage removal by laser thermal annealing

Method of making a memory cell with polished insulator layer

Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same