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Inventor profile of:

Eric Neyret

City:

Sassenage

Country:

France

Published Applications:

Last publication date:

2015-08-06

Top Assignees for applications by Eric Neyret

The entities that hold a legal rights for patent applications filed by inventor Neyret Eric:

S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES 10 Bernin, France
S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES, S.A. 8 Bernin, France
S.O.I Tec Silicon on Insulator Technologies 2 Bernin, France
SOITEC 2 Bernin, France
S.O.I TEC Silicon on Insulator Technologies S.A. 1 Crolles Cedex, France
S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES S.A., a French corporate 1 Bernin, France
S.O.I. TEC Silicon on Insulator Technologies S.A. 1 Bernin, France
S.O.I.Tec Silicon on Insulator Technologies S.A., a French corporate 1 Bernin, France

Recent patent applications by Neyret Eric

Eric Neyret from Sassenage, FR has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2015-08-06

US20150221545A1

Electricity

METHOD FOR REDUCING SURFACE ROUGHNESS WHILE PRODUCING A HIGH QUALITY USEFUL LAYER

#2 | 2011-09-29

US20110233720A1

Electricity

Treatment for bonding interface stabilization

#3 | 2011-05-19

US20110117691A1

Electricity

MIXED TRIMMING METHOD

#4 | 2011-04-28

US20110097874A1

Electricity

Progressive trimming method

#5 | 2011-04-28

US20110097871A1

Electricity

Process for the transfer of a thin layer formed in a substrate with vacancy clusters

#6 | 2010-03-04

US20100052092A1

Electricity

Method for fabricating a semiconductor on insulator substrate with reduced Secco defect density

#7 | 2009-02-05

US20090035920A1

Electricity

Process for fabricating a substrate of the silicon-on-insulator type with reduced roughness and uniform thickness

#8 | 2008-08-07

US20080188060A1

Electricity

Process for fabricating a substrate of the silicon-on-insulator type with thin surface layer

#9 | 2008-01-17

US20080014718A1

Electricity

Treatment for bonding interface stabilization

#10 | 2008-01-17

US20080014713A1

Electricity

Treatment for bonding interface stabilization

#11 | 2007-12-27

US20070298606A1

Performing operations; transporting

CHEMICAL-MECHANICAL POLISHING METHOD AND APPARATUS

#12 | 2007-09-20

US20070216042A1

Electricity

Methods for manufacturing compound-material wafers and for recycling used donor substrates

#13 | 2007-06-28

US20070148910A1

Electricity

Finishing process for the manufacture of a semiconductor structure

#14 | 2006-11-21

US10671813

Method for minimizing slip line faults on a semiconductor wafer surface

#15 | 2006-10-05

US20060223283A1

Electricity

Method for producing a high quality useful layer on a substrate

#16 | 2006-08-03

US20060172508A1

Electricity

Process for transfer of a thin layer formed in a substrate with vacancy clusters

#17 | 2006-06-29

US20060141755A1

Electricity

Method of configuring a process to obtain a thin layer with a low density of holes

#18 | 2006-02-16

US20060035445A1

Electricity

Method of reducing the surface roughness of a semiconductor wafer

#19 | 2006-02-02

US20060024908A1

Electricity

Method of reducing the surface roughness of a semiconductor wafer

#20 | 2005-11-08

US10750443

Method for reducing free surface roughness of a semiconductor wafer

#21 | 2005-10-20

US20050230754A1

Electricity

Preventive treatment method for a multilayer semiconductor wafer

#22 | 2005-09-15

US20050202658A1

Electricity

Method for limiting slip lines in a semiconductor substrate

#23 | 2005-09-06

US10784040

Preventive treatment method for a multilayer semiconductor wafer

#24 | 2005-06-07

US10754930

Method for preparing a semiconductor wafer surface

#25 | 2005-05-05

US20050094990A1

Electricity

Heat treatment for edges of multilayer semiconductor wafers

#26 | 2005-02-08

US10700885

Heat treatment for edges of multilayer semiconductor wafers

#27 | 2005-02-03

US20050026426A1

Electricity

Method for producing a high quality useful layer on a substrate utilizing helium and hydrogen implantations

InventorID:

1250848 ⎘