Assignee profile:

S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES, S.A.

City:

Bernin

Country:

France

Published Applications:

84

Last publication date:

2012-07-26

Patent Grants:

81

Last grant date:

2013-07-02

Top Inventors for applications by S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES, S.A.

These are the the leading inventors for applications assigned to S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES, S.A.:

Recent patent applications by S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES, S.A.

S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES, S.A. based in Bernin, FR has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:

#1 | 2012-07-26
US20120187541A1
Electricity

EPITAXIAL METHODS FOR REDUCING SURFACE DISLOCATION DENSITY IN SEMICONDUCTOR MATERIALS

#2 | 2010-11-04 βœ… Patent 8,476,148 granted on 2013-07-02
US20100279487A1
Electricity

Method for transferring a layer from a donor substrate onto a handle substrate

#3 | 2010-09-30 βœ… Patent 8,178,427 granted on 2012-05-15
US20100244197A1
Electricity

Epitaxial methods for reducing surface dislocation density in semiconductor materials

#4 | 2010-07-29
US20100187568A1
Electricity

EPITAXIAL METHODS AND STRUCTURES FOR FORMING SEMICONDUCTOR MATERIALS

#5 | 2010-07-22 βœ… Patent 8,324,075 granted on 2012-12-04
US20100181653A1
Electricity

Methods for recycling substrates and fabricating laminated wafers

#6 | 2010-06-10 βœ… Patent 8,461,055 granted on 2013-06-11
US20100140746A1
Electricity

Process for preparing cleaned surfaces of strained silicon

#7 | 2010-05-27 βœ… Patent 8,679,942 granted on 2014-03-25
US20100127353A1
Electricity

Strain engineered composite semiconductor substrates and methods of forming same

#8 | 2010-05-06 βœ… Patent 8,278,193 granted on 2012-10-02
US20100109126A1
Electricity

Methods of forming layers of semiconductor material having reduced lattice strain, semiconductor structures, devices and engineered substrates including same

#9 | 2010-01-14 βœ… Patent 7,825,401 granted on 2010-11-02
US20100006893A1
Electricity

Strained layers within semiconductor buffer structures

#10 | 2007-06-28 βœ… Patent 7,892,946 granted on 2011-02-22
US20070148915A1
Performing operations; transporting

Device and method for cutting an assembly

#11 | 2007-05-31 βœ… Patent 7,406,994 granted on 2008-08-05
US20070122926A1
Electricity

Substrate layer cutting device and method

#12 | 2007-05-31 βœ… Patent 8,083,115 granted on 2011-12-27
US20070119893A1
Electricity

Substrate cutting device and method

#13 | 2007-05-10
US20070105246A1
Electricity

METHOD OF MANUFACTURING A MATERIAL COMPOUND WAFER

#14 | 2007-05-10 βœ… Patent 7,439,160 granted on 2008-10-21
US20070104240A1
Electricity

Methods for producing a semiconductor entity

#15 | 2007-04-26 βœ… Patent 7,740,735 granted on 2010-06-22
US20070093039A1
Electricity

Tools and methods for disuniting semiconductor wafers

#16 | 2007-03-13 βœ… Patent 7,189,304 granted on 2007-03-13
US10681566
-

Substrate layer cutting device and method

#17 | 2007-03-06 βœ… Patent 7,187,162 granted on 2007-03-06
US10733470
-

Tools and methods for disuniting semiconductor wafers

#18 | 2007-01-16 βœ… Patent 7,163,897 granted on 2007-01-16
US10637073
-

Method for assaying elements in a substrate for optics, electronics, or optoelectronics

#19 | 2006-12-21 βœ… Patent 7,407,867 granted on 2008-08-05
US20060286770A1
Electricity

Method for concurrently producing at least a pair of semiconductor structures that each include at least one useful layer on a substrate

#20 | 2006-12-21 βœ… Patent 7,225,095 granted on 2007-05-29
US20060284720A1
Electricity

Thermal processing equipment calibration method

#21 | 2006-11-21 βœ… Patent 7,138,344 granted on 2006-11-21
US10671813
-

Method for minimizing slip line faults on a semiconductor wafer surface

#22 | 2006-10-17 βœ… Patent 7,122,095 granted on 2006-10-17
US10800252
-

Methods for forming an assembly for transfer of a useful layer

#23 | 2006-10-03 βœ… Patent 7,115,481 granted on 2006-10-03
US10686084
-

Method for concurrently producing at least a pair of semiconductor structures that each include at least one useful layer on a substrate

#24 | 2006-09-28 βœ… Patent 7,405,135 granted on 2008-07-29
US20060216849A1
Electricity

Substrate for stressed systems and method of making same

#25 | 2006-08-29 βœ… Patent 7,098,148 granted on 2006-08-29
US10863352
-

Method for heat treating a semiconductor wafer

#26 | 2006-08-22 βœ… Patent 7,094,668 granted on 2006-08-22
US10716612
-

Annealing process and device of semiconductor wafer

#27 | 2006-07-04 βœ… Patent 7,071,077 granted on 2006-07-04
US10808288
-

Method for preparing a bonding surface of a semiconductor layer of a wafer

#28 | 2006-06-15 βœ… Patent 7,736,988 granted on 2010-06-15
US20060128117A1
Electricity

Forming structures that include a relaxed or pseudo-relaxed layer on a substrate

#29 | 2006-06-06 βœ… Patent 7,056,809 granted on 2006-06-06
US10695938
-

Method for ion treating a semiconductor material for subsequent bonding

#30 | 2006-05-25 βœ… Patent 7,229,898 granted on 2007-06-12
US20060110899A1
Electricity

Methods for fabricating a germanium on insulator wafer

#31 | 2006-05-04 βœ… Patent 7,135,383 granted on 2006-11-14
US20060091400A1
Electricity

Composite structure with high heat dissipation

#32 | 2006-04-27 βœ… Patent 7,232,743 granted on 2007-06-19
US20060088979A1
Electricity

Semiconductor structure for providing strained crystalline layer on insulator and method for fabricating same

#33 | 2006-04-25 βœ… Patent 7,033,905 granted on 2006-04-25
US10726039
-

Recycling of a wafer comprising a buffer layer after having separated a thin layer therefrom by mechanical means

#34 | 2006-04-18 βœ… Patent 7,029,993 granted on 2006-04-18
US10069058
-

Method for treating substrates for microelectronics and substrates obtained according to said method

#35 | 2006-04-13 βœ… Patent 7,163,873 granted on 2007-01-16
US20060079070A1
Electricity

Substrate for stressed systems and method of making same

#36 | 2006-04-13 βœ… Patent 7,145,214 granted on 2006-12-05
US20060076649A1
Electricity

Substrate for stressed systems and method of making same

#37 | 2006-04-13 βœ… Patent 7,378,729 granted on 2008-05-27
US20060076578A1
Electricity

Recycling a wafer comprising a buffer layer, after having separated a thin layer therefrom

#38 | 2006-04-04 βœ… Patent 7,022,586 granted on 2006-04-04
US10728343
-

Method for recycling a substrate

#39 | 2006-03-28 βœ… Patent 7,018,909 granted on 2006-03-28
US10784016
-

Forming structures that include a relaxed or pseudo-relaxed layer on a substrate

#40 | 2006-03-28 βœ… Patent 7,017,570 granted on 2006-03-28
US10775865
-

Apparatus and method for splitting substrates

#41 | 2006-03-28 βœ… Patent 7,018,910 granted on 2006-03-28
US10614327
-

Transfer of a thin layer from a wafer comprising a buffer layer

#42 | 2006-03-23 βœ… Patent 7,535,115 granted on 2009-05-19
US20060060922A1
Electricity

Wafer and method of producing a substrate by transfer of a layer that includes foreign species

#43 | 2006-03-07 βœ… Patent 7,008,857 granted on 2006-03-07
US10764289
-

Recycling a wafer comprising a buffer layer, after having separated a thin layer therefrom

#44 | 2006-03-07 βœ… Patent 7,009,270 granted on 2006-03-07
US10755007
-

Substrate for stressed systems and method of making same

#45 | 2006-03-07 βœ… Patent 7,008,859 granted on 2006-03-07
US10678127
-

Wafer and method of producing a substrate by transfer of a layer that includes foreign species

#46 | 2006-02-21 βœ… Patent 7,001,826 granted on 2006-02-21
US10663917
-

Wafer with a relaxed useful layer and method of forming the wafer

#47 | 2006-02-07 βœ… Patent 6,995,427 granted on 2006-02-07
US10763978
-

Semiconductor structure for providing strained crystalline layer on insulator and method for fabricating same

#48 | 2006-01-31 βœ… Patent 6,991,995 granted on 2006-01-31
US10784032
-

Method of producing a semiconductor structure having at least one support substrate and an ultrathin layer

#49 | 2006-01-24 βœ… Patent 6,989,314 granted on 2006-01-24
US10777721
-

Semiconductor structure and method of making same

#50 | 2006-01-24 βœ… Patent 6,988,936 granted on 2006-01-24
US10621122
-

Surface preparation for receiving processing treatments

#51 | 2006-01-17 βœ… Patent 6,987,051 granted on 2006-01-17
US10733729
-

Method of making cavities in a semiconductor wafer

#52 | 2005-12-15 βœ… Patent 7,138,325 granted on 2006-11-21
US20050277278A1
Electricity

Method of manufacturing a wafer

#53 | 2005-12-01 βœ… Patent 7,262,113 granted on 2007-08-28
US20050266659A1
Electricity

Methods for transferring a useful layer of silicon carbide to a receiving substrate

#54 | 2005-11-15 βœ… Patent 6,964,914 granted on 2005-11-15
US10349295
-

Method of manufacturing a free-standing substrate made of monocrystalline semi-conductor material

#55 | 2005-11-08 βœ… Patent 6,962,858 granted on 2005-11-08
US10750443
-

Method for reducing free surface roughness of a semiconductor wafer

#56 | 2005-10-25 βœ… Patent 6,958,284 granted on 2005-10-25
US10617521
-

Method of smoothing the outline of a useful layer of material transferred onto a support substrate

#57 | 2005-10-20 βœ… Patent 7,190,029 granted on 2007-03-13
US20050230754A1
Electricity

Preventive treatment method for a multilayer semiconductor wafer

#58 | 2005-10-18 βœ… Patent 6,955,971 granted on 2005-10-18
US10704703
-

Semiconductor structure and methods for fabricating same

#59 | 2005-10-11 βœ… Patent 6,953,736 granted on 2005-10-11
US10615259
-

Process for transferring a layer of strained semiconductor material

#60 | 2005-09-22 βœ… Patent 7,235,427 granted on 2007-06-26
US20050208322A1
Electricity

Method for treating substrates for microelectronics and substrates obtained by said method

#61 | 2005-09-20 βœ… Patent 6,946,317 granted on 2005-09-20
US10700899
-

Method of fabricating heteroepitaxial microstructures

#62 | 2005-09-15 βœ… Patent 7,001,832 granted on 2006-02-21
US20050202658A1
Electricity

Method for limiting slip lines in a semiconductor substrate

#63 | 2005-09-06 βœ… Patent 6,939,783 granted on 2005-09-06
US10784040
-

Preventive treatment method for a multilayer semiconductor wafer

#64 | 2005-09-01 βœ… Patent 6,991,956 granted on 2006-01-31
US20050191825A1
Electricity

Methods for transferring a thin layer from a wafer having a buffer layer

#65 | 2005-08-30 βœ… Patent 6,936,523 granted on 2005-08-30
US10733431
-

Two-stage annealing method for manufacturing semiconductor substrates

#66 | 2005-08-30 βœ… Patent 6,936,482 granted on 2005-08-30
US10320063
-

Method of fabricating substrates and substrates obtained by this method

#67 | 2005-07-14 βœ… Patent 7,221,038 granted on 2007-05-22
US20050151155A1
Electricity

Method of fabricating substrates and substrates obtained by this method

#68 | 2005-06-07 βœ… Patent 6,903,032 granted on 2005-06-07
US10754930
-

Method for preparing a semiconductor wafer surface

#69 | 2005-06-07 βœ… Patent 6,902,988 granted on 2005-06-07
US10318304
-

Method for treating substrates for microelectronics and substrates obtained by said method

#70 | 2005-05-26 βœ… Patent 7,041,577 granted on 2006-05-09
US20050112885A1
Electricity

Process for manufacturing a substrate and associated substrate

#71 | 2005-05-12 βœ… Patent 7,071,029 granted on 2006-07-04
US20050101105A1
Electricity

Methods for fabricating final substrates

#72 | 2005-05-12 βœ… Patent 7,300,856 granted on 2007-11-27
US20050101104A1
Electricity

Process for detaching layers of material

#73 | 2005-05-05 βœ… Patent 7,049,250 granted on 2006-05-23
US20050094990A1
Electricity

Heat treatment for edges of multilayer semiconductor wafers

#74 | 2005-03-31 βœ… Patent 7,078,353 granted on 2006-07-18
US20050070078A1
Electricity

Indirect bonding with disappearance of bonding layer

#75 | 2005-03-03 βœ… Patent 7,189,632 granted on 2007-03-13
US20050048739A1
Electricity

Multifunctional metallic bonding

#76 | 2005-02-10 βœ… Patent 6,974,760 granted on 2005-12-13
US20050032330A1
Electricity

Methods for transferring a useful layer of silicon carbide to a receiving substrate

#77 | 2005-02-03 βœ… Patent 7,081,399 granted on 2006-07-25
US20050026426A1
Electricity

Method for producing a high quality useful layer on a substrate utilizing helium and hydrogen implantations

#78 | 2005-02-03 βœ… Patent 7,169,683 granted on 2007-01-30
US20050026391A1
Electricity

Preventive treatment method for a multilayer semiconductor structure

#79 | 2005-01-27 βœ… Patent 7,060,620 granted on 2006-06-13
US20050020084A1
Performing operations; transporting

Method of preparing a surface of a semiconductor wafer to make it epiready

#80 | 2005-01-13 βœ… Patent 7,018,913 granted on 2006-03-28
US20050009348A1
Electricity

Method for implanting atomic species through an uneven surface of a semiconductor layer

#81 | 2005-01-13 βœ… Patent 6,982,210 granted on 2006-01-03
US20050009296A1
Electricity

Method for manufacturing a multilayer semiconductor structure that includes an irregular layer

#82 | 2005-01-13 βœ… Patent 7,067,393 granted on 2006-06-27
US20050006740A1
Electricity

Substrate assembly for stressed systems

#83 | 2005-01-06 βœ… Patent 7,182,234 granted on 2007-02-27
US20050000649A1
Electricity

Substrate cutting device and method

#84 | 2005-01-04 βœ… Patent 6,838,358 granted on 2005-01-04
US10716900
-

Method of manufacturing a wafer

AssigneeID:

186997 ⎘