Mountain View, California
United States
93
2026-04-30
The entities that hold a legal rights for patent applications filed by inventor Walker Andrew J.:
Andrew J. Walker from Mountain View, US has applied for patents for these inventions. The list has both pending applications and granted patents:
METHOD AND SYSTEM FOR ROUTING OF ELECTRICAL CONDUCTORS OVER NEUTRALIZED POWER FETS
#2 | 2026-02-26VERTICAL FIN-BASED FIELD EFFECT TRANSISTOR (FINFET) WITH NEUTRALIZED FIN TIPS
#3 | 2025-02-13METHOD AND SYSTEM FOR A FIN-BASED VOLTAGE CLAMP
#4 | 2022-10-27Three dimensional perpendicular magnetic tunnel junction with thin film transistor array
#5 | 2022-07-14High density spin orbit torque magnetic random access memory
#6 | 2022-06-16DRAM with selective epitaxial cell transistor
#7 | 2022-06-16Compact and efficient CMOS inverter
#8 | 2021-12-16Selector transistor with metal replacement gate wordline
#9 | 2021-09-30DRAM with selective epitaxial transistor and buried bitline
#10 | 2021-09-30Compact and efficient CMOS inverter
#11 | 2021-07-29DRAM with selective epitaxial cell transistor
#12 | 2021-07-15Selector transistor with continuously variable current drive
#13 | 2021-03-25Integration of epitaxially grown channel selector with two terminal resistive switching memory element
#14 | 2021-03-04Integration of epitaxially grown channel selector with MRAM device
#15 | 2020-12-01Vertical selector stt-MRAM architecture
#16 | 2020-11-17Vertical selector STT-MRAM architecture
#17 | 2020-04-23MEMORY CELL USING SELECTIVE EPITAXIAL VERTICAL CHANNEL MOS SELECTOR TRANSISTOR
#18 | 2020-01-09High density MRAM integration
#19 | 2020-01-09High density MRAM integration
#20 | 2019-11-21Three dimensional perpendicular magnetic tunnel junction with thin film transistor array
#21 | 2019-07-11Fabrication of a perpendicular magnetic tunnel junction (PMTJ) using block copolymers
#22 | 2019-07-04VERTICAL COMPOUND SEMICONDUCTOR FOR USE WITH A PERPENDICULAR MAGNETIC TUNNEL JUNCTION (PMTJ)
#23 | 2019-07-04Fabrication methods of forming cylindrical vertical SI etched channel 3D switching devices
#24 | 2019-07-04Perpendicular magnetic tunnel junction memory cells having vertical channels
#25 | 2019-07-04Methods of forming perpendicular magnetic tunnel junction memory cells having vertical channels
#26 | 2019-07-04Vertically-strained silicon device for use with a perpendicular magnetic tunnel junction (PMTJ)
#27 | 2019-07-04Annular vertical Si etched channel MOS devices
#28 | 2019-07-04Fabrication methods of forming annular vertical SI etched channel MOS devices
#29 | 2019-07-04Steep slope field-effect transistor (FET) for a perpendicular magnetic tunnel junction (PMTJ)
#30 | 2019-07-04Three dimensional perpendicular magnetic junction with thin-film transistor
#31 | 2019-07-04Method of making a three dimensional perpendicular magnetic tunnel junction with thin-film transistor
#32 | 2019-07-04Methods of forming perpendicular magnetic tunnel junction memory cells having vertical channels
#33 | 2019-07-04Perpendicular magnetic tunnel junction memory cells having shared source contacts
#34 | 2019-07-04Cylindrical vertical SI etched channel 3D switching devices
#35 | 2019-03-26Steep slope field-effect transistor (FET) for a perpendicular magnetic tunnel junction (PMTJ)
#36 | 2019-01-22Buried tap for a vertical transistor used with a perpendicular magnetic tunnel junction (PMTJ)
#37 | 2017-09-28MONOLITHIC 3-D DYNAMIC MEMORY AND METHOD
#38 | 2017-01-26Independent vertical-gate 3-D NAND memory circuit
#39 | 2016-04-07NON-VOLATILE MEMORY DEVICES WITH THIN-FILM AND MONO-CRYSTALLINE SILICON TRANSISTORS
#40 | 2014-05-27ESD protection device with charge collections regions
#41 | 2012-10-02Voltage protection device
#42 | 2012-09-06Dense arrays and charge storage devices
#43 | 2011-06-30DENSE ARRAYS AND CHARGE STORAGE DEVICES
#44 | 2011-01-27Method for forming doped polysilicon via connecting polysilicon layers
#45 | 2010-11-23Circuits providing ESD protection to high voltage laterally diffused metal oxide semiconductor (LDMOS) transistors
#46 | 2010-06-10STACKED DUAL-GATE NMOS DEVICES WITH ANTIMONY SOURCE-DRAIN REGIONS AND METHODS FOR MANUFACTURING THEREOF
#47 | 2010-02-09Silicon controlled rectifier electrostatic discharge clamp for a high voltage laterally diffused MOS transistor
#48 | 2009-11-10Two mask floating gate EEPROM and method of making
#49 | 2009-10-15Method for forming doped polysilicon via connecting polysilicon layers
#50 | 2009-07-30DUAL-GATE MEMORY DEVICE WITH CHANNEL CRYSTALLIZATION FOR MULTIPLE LEVELS PER CELL (MLC)
#51 | 2009-04-09DUAL-GATE MEMORY DEVICE WITH CHANNEL CRYSTALLIZATION FOR MULTIPLE LEVELS PER CELL (MLC)
#52 | 2009-04-02RETENTION IMPROVEMENT IN DUAL-GATE MEMORY
#53 | 2009-03-26ERASE METHOD IN THIN FILM NONVOLATILE MEMORY
#54 | 2009-03-17Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same
#55 | 2009-03-12Methods to Prevent Program Disturb in Nonvolatile Memory
#56 | 2008-12-25DUAL-GATE DEVICE AND METHOD
#57 | 2008-12-25Dual-gate device
#58 | 2008-11-20NONVOLATILE MEMORY WITH BACKPLATE
#59 | 2008-11-20Nonvolatile memory with backplate
#60 | 2008-11-20DUAL-GATE NMOS DEVICES WITH ANTIMONY SOURCE-DRAIN REGIONS AND METHODS FOR MANUFACTURING THEREOF
#61 | 2008-11-20NONVOLATILE MEMORY WITH MULTIPLE BITS PER CELL
#62 | 2008-04-10Dual-gate device
#63 | 2008-04-10DUAL-GATE MEMORY DEVICE AND OPTIMIZATION OF ELECTRICAL INTERACTION BETWEEN FRONT AND BACK GATES TO ENABLE SCALING
#64 | 2007-12-13Dual-gate semiconductor devices with enhanced scalability
#65 | 2007-10-18NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same
#66 | 2007-09-20Memory array incorporating mirrored NAND strings and non-shared global bit lines within a block
#67 | 2007-06-19NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same
#68 | 2007-06-14Dual-gate nonvolatile memory and method of program inhibition
#69 | 2007-06-07Dual-gate device and method
#70 | 2007-05-03Dual-gate device and method
#71 | 2007-02-08Dual-gate device and method
#72 | 2006-11-09TFT mask ROM and method for making same
#73 | 2006-10-31Dense arrays and charge storage devices
#74 | 2006-06-01Dual-gate device and method
#75 | 2006-04-06Junction diode comprising varying semiconductor compositions
#76 | 2006-04-06Doped polysilicon via connecting polysilicon layers
#77 | 2006-02-28Method for fabricating programmable memory array structures incorporating series-connected transistor strings
#78 | 2006-01-31Rail stack array of charge storage devices and method of making same
#79 | 2005-11-01Formation of thin channels for TFT devices to ensure low variability of threshold voltages
#80 | 2005-09-06High density 3d rail stack arrays and method of making
#81 | 2005-06-16Nand memory array incorporating multiple series selection devices and method for operation of same
#82 | 2005-06-09NAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of same
#83 | 2005-06-09Memory array incorporating memory cells arranged in NAND strings
#84 | 2005-05-24Two mask floating gate EEPROM and method of making
#85 | 2005-05-03Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication
#86 | 2005-04-19Monolithic three dimensional array of charge storage devices containing a planarized surface
#87 | 2005-04-14Semiconductor device with localized charge storage dielectric and method of making same
#88 | 2005-03-31TFT mask ROM and method for making same
#89 | 2005-03-24Storage layer optimization of a nonvolatile memory device
#90 | 2005-03-10Nonvolatile memory cell without a dielectric antifuse having high- and low-impedance states
#91 | 2005-02-22Thin film transistor with metal oxide layer and method of making same
#92 | 2005-02-01Semiconductor device with localized charge storage dielectric and method of making same
#93 | 2005-01-11TFT mask ROM and method for making same
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