SanDisk 3D LLC

ReRAM MIM structure formation

Scan chain circuits in non-volatile memory

Multiple junction thin film transistor

Vertical bit line non-volatile memory with recessed word lines

Sense amplifier with integrating capacitor and methods of operation

Independent sense amplifier addressing and quota sharing in non-volatile memory

Method for forming a doped metal oxide for use in resistive switching memory elements

Two stage forming of resistive random access memory cells

Memory array having divided apart bit lines and partially divided bit line selector switches

Monolithic three dimensional memory arrays with staggered vertical bit line select transistors and methods therfor

Independent set/reset programming scheme

High endurance non-volatile storage

Low forming voltage non-volatile storage device

Sense amplifier including a single-transistor amplifier and level shifter and methods therefor

Monolithic three dimensional memory arrays with staggered vertical bit lines and dual-gate bit line select transistors

Dual gate structure

Apparatus and methods for sensing hard bit and soft bits

Vertical bit line non-volatile memory systems and methods of fabrication

Conductive barriers for ternary nitride thin-film resistors

Multiple layer forming scheme for vertical cross point reram

Timed multiplex sensing

ReRAM cells with diffusion-resistant metal silicon oxide layers

Shaping ReRAM conductive filaments by controlling grain-boundary density

Current-limiting electrodes

Side wall bit line structures

Memory hole bit line structures

Controlling adjustable resistance bit lines connected to word line combs

Setting channel voltages of adjustable resistance bit line structures using dummy word lines

Intrinsic vertical bit line architecture

Vertical TFT with tunnel barrier

Single-stage folded cascode buffer amplifiers with analog comparators

Dual capacitor sense amplifier and methods therefor

Resistance-switching memory cell with multiple raised structures in a bottom electrode

Dielectric-based memory cells having multi-level one-time programmable and bi-level rewriteable operating modes and methods of forming the same

Three dimensional non-volatile storage with connected word lines

Capping thin-film resistors to control interface oxidation

Resistive random access memory cells having shared electrodes with transistor devices

Vertical bit line wide band gap TFT decoder

Multi-level memory array having resistive elements for multi-bit data storage

Transistor device with gate bottom isolation and method of making thereof

Dual channel vertical field effect transistor including an embedded electrode

Vertical thin film transistor selection devices and methods of fabrication

Method for forming oxide below control gate in vertical channel thin film transistor

Vertical thin film transistors in non-volatile storage systems

Non-volatile storage system biasing conditions for standby and first read

Non-volatile 3D memory with cell-selectable word line decoding

Timed multiplex sensing

Transition metal oxide bilayers

Trench multilevel contact to a 3D memory array and method of making thereof

Embedded resistors for resistive random access memory cells

Atomic layer deposition of metal oxides for memory applications

Multilevel contact to a 3D memory array and method of making thereof

Resistive random access memory cell having three or more resistive states

Method of operating FET low current 3D re-ram

Nonvolatile memory device having a current limiting element

Morphology control of ultra-thin MeOx layer

Methods of forming sidewall gates

Plasma reduction method for modifying metal oxide stoichiometry in ReRAM

Vertical 1T-1R memory cells, memory arrays and methods of forming the same

Method for forming metal oxides and silicides in a memory device

Doped oxide dielectrics for resistive random access memory cells

Method of operating FET low current 3D Re-RAM

Vertical bit line wide band gap TFT decoder

Method of forming anneal-resistant embedded resistor for non-volatile memory application

Controlling composition of multiple oxides in resistive switching layers using atomic layer deposition

Atomic layer deposition of metal oxide materials for memory applications

Dense arrays and charge storage devices

Bipolar multistate nonvolatile memory

Shared-gate vertical-TFT for vertical bit line array

Confined defect profiling within resistive random memory access cells

Compensation scheme for non-volatile memory

Compensation scheme for non-volatile memory

Morphology control of ultra-thin MeOx layer

Metal aluminum nitride embedded resistors for resistive random memory access cells

High capacity select switches for three-dimensional structures

Multifunctional electrode

Differential current sense amplifier and method for non-volatile memory

Method of forming anneal-resistant embedded resistor for non-volatile memory application

Atomic layer deposition of metal oxides for memory applications

Methods and systems to reduce location-based variations in switching characteristics of 3D ReRAM arrays

ReRAM materials stack for low-operating-power and high-density applications

Sense amplifier local feedback to control bit line voltage

Multi-level memory arrays with memory cells that employ bipolar storage elements and methods of forming the same

Non-volatile memory having 3D array of read/write elements with vertical bit lines and select devices and methods thereof

Controlling composition of multiple oxides in resistive switching layers using atomic layer deposition

Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning

Sequential atomic layer deposition of electrodes and resistive switching components

Resistive random access memory cells having metal alloy current limiting layers

Multiple layer forming scheme for vertical cross point reram

Vertical cross point reram forming method

Memory device having an integrated two-terminal current limiting resistor

Memory cells having storage elements that share material layers with steering elements and methods of forming the same

Dynamic address grouping for parallel programming in non-volatile memory