Inventor profile of:

Joe Margetis

City:

Gilbert, Arizona

Country:

United States

Published Applications:

34

Last publication date:

2026-05-28

Top Assignees for applications by Joe Margetis

The entities that hold a legal rights for patent applications filed by inventor Margetis Joe:

Recent patent applications by Margetis Joe

Joe Margetis from Gilbert, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-05-28
US20260150594A1
Electricity

COMBINATORIAL PRECURSOR CHEMISTRY FOR LOW TEMPERATURE

#2 | 2026-05-14
US20260136521A1
Electricity

REDUCED STRAIN Si/SiGe HETEROEPITAXY STACKS FOR 3D DRAM

#3 | 2026-03-05
US20260068564A1
Electricity

CYCLIC PROCESSING METHODS FOR DEFECT REDUCTION, AND RELATED APPARATUS, DEVICES, AND PROCESSING CHAMBERS

#4 | 2026-02-05
US20260040839A1
Electricity

METHODS OF EPITAXIALLY GROWING BORON-CONTAINING STRUCTURES

#5 | 2025-12-04
US20250372373A1
Electricity

GATE-ALL-AROUND (GAA) INTERFACE MODIFICATIONS TO IMPROVE ABRUPTNESS

#6 | 2025-11-27
US20250361647A1
Chemistry; metallurgy

UV ENERGY SOURCES FOR PROCESSING CHAMBERS, AND RELATED APPARATUS AND METHODS

#7 | 2025-11-20
US20250354291A1
Chemistry; metallurgy

INHIBITORS FOR SELECTIVE EPITAXIAL DEPOSITION

#8 | 2025-08-28
US20250273464A1
Electricity

METHOD FOR DEPOSITING BORON AND GALLIUM CONTAINING SILICON GERMANIUM LAYERS

#9 | 2024-10-03
US20240332016A1
Electricity

METHODS FOR SILICON GERMANIUM UNIFORMITY CONTROL USING MULTIPLE PRECURSORS

#10 | 2024-08-15
US20240274437A1
Electricity

METHODS OF FORMING STRUCTURES INCLUDING SILICON GERMANIUM AND SILICON LAYERS, DEVICES FORMED USING THE METHODS, AND SYSTEMS FOR PERFORMING THE METHODS

#11 | 2024-05-02
US20240145242A1
Electricity

METHOD OF BLOCKING DIELECTRIC SURFACES USING BLOCKING MOLECULES TO ENABLE SELECTIVE EPI DEPOSITION

#12 | 2024-05-02
US20240145241A1
Electricity

SURFACE MODIFIERS FOR ENHANCED EPITAXIAL NUCLEATION AND WETTING

#13 | 2023-07-13
US20230223257A1
Electricity

METHODS OF EPITAXIALLY GROWING BORON-CONTAINING STRUCTURES

#14 | 2023-05-11
US20230145240A1
Electricity

METHODS FOR SELECTIVE DEPOSITION UTILIZING N-TYPE DOPANTS AND/OR ALTERNATIVE DOPANTS TO ACHIEVE HIGH DOPANT INCORPORATION

#15 | 2023-01-26
US20230029344A1
Electricity

METHODS OF FORMATION OF A SIGE/SI SUPERLATTICE

#16 | 2023-01-19
US20230012819A1
Electricity

REDUCED STRAIN Si/SiGe HETEROEPITAXY STACKS FOR 3D DRAM

#17 | 2022-09-29
US20220310825A1
Electricity

METHOD FOR DEPOSITING A GROUP IV SEMICONDUCTOR AND RELATED SEMICONDUCTOR DEVICE STRUCTURES

#18 | 2021-12-02
US20210375622A1
Electricity

METHOD FOR DEPOSITING BORON AND GALLIUM CONTAINING SILICON GERMANIUM LAYERS

#19 | 2021-11-18
US20210358741A1
Electricity

Methods for silicon germanium uniformity control using multiple precursors

#20 | 2021-10-21
US20210327704A1
Electricity

Methods of forming structures including silicon germanium and silicon layers, devices formed using the methods, and systems for performing the methods

#21 | 2021-02-04
US20210035802A1
Electricity

Methods for selective deposition utilizing n-type dopants and/or alternative dopants to achieve high dopant incorporation

#22 | 2020-07-16
US20200224309A1
Chemistry; metallurgy

Temperature-controlled flange and reactor system including same

#23 | 2020-03-12
US20200083375A1
Electricity

Method for depositing a group IV semiconductor and related semiconductor device structures

#24 | 2020-01-02
US20200002811A1
Chemistry; metallurgy

Temperature-controlled flange and reactor system including same

#25 | 2019-01-24
US20190027605A1
Electricity

Method for depositing a group IV semiconductor and related semiconductor device structures

#26 | 2019-01-24
US20190027584A1
Electricity

Method for selectively depositing a Group IV semiconductor and related semiconductor device structures

#27 | 2019-01-24
US20190027583A1
Electricity

Method for depositing a group IV semiconductor and related semiconductor device structures

#28 | 2019-01-10
US20190013199A1
Electricity

Methods for forming a silicon germanium tin layer and related semiconductor device structures

#29 | 2018-11-08
US20180323059A1
Electricity

Methods for forming silicon-containing epitaxial layers and related semiconductor device structures

#30 | 2018-05-31
US20180151358A1
Electricity

Process for forming a film on a substrate using multi-port injection assemblies

#31 | 2017-12-28
US20170372884A1
Electricity

Formation of epitaxial layers via dislocation filtering

#32 | 2017-09-28
US20170278707A1
Electricity

Radial and thickness control via biased multi-port injection settings

#33 | 2017-06-01
US20170154770A1
Electricity

Methods of forming silicon germanium tin films and structures and devices including the films

#34 | 2017-02-16
US20170047446A1
Electricity

Methods of forming highly p-type doped germanium tin films and structures and devices including the films

InventorID:

1800729 ⎘