Junli Wang

AIR-GAP ISOLATED STACKED SEMICONDUCTOR DEVICE ARCHITECTURE

STACKED FIELD-EFFECT TRANSISTOR (FET) WITHOUT PLACEHOLDER

SELF-ALIGNED BACKSIDE CONTACT FORMATION FOR STACKED FET

FINFET DEVICES

STACKED DEVICE CONTACT CONFIGURATIONS FOR STAGGERED SOURCE/DRAIN REGIONS

BULK NANOSHEET WITH DIELECTRIC ISOLATION

SEMICONDUCTOR DEVICE WITH I/O DEVICE AT GATE MODULE

STRESS GENERATION IN STACKED NANOSHEET ARCHITECTURES

STACKED FET WITH FLEXIBLE INTER-EPI DIELECTRIC THICKNESS

MULTI-THRESHOLD VOLTAGE STACK OF A STACKED FIELD EFFECT TRANSISTOR

GATE INTERCONNECTING STRUCTURES FOR STACKED FIELD-EFFECT TRANSISTORS

L-SHAPED STACKED FIELD EFFECT TRANSISTOR

STACKED SEMICONDUCTOR STRUCTURE WITH OPPOSITE POLARITY TRANSISTORS

SELF-ALIGNED GATE CUT STRUCTURE

SIDEWALL PINCH-OFF OF WORK FUNCTION METAL

SHAPED EPITAXY

DIELECTRIC INNER SPACERS FOR NANOSHEET TRANSISTORS

STACKED TRANSISTORS WITH VERTICALLY STAGGERED CONTACT VIAS

STACKED TRANSISTORS WITH DISCONTINUOUS HIGH-K ON VERTICAL GATE SPACERS

SCALED STACKED FET USING COMBINED STRUCTURES IN ADJACENT CELLS

STACKED TRANSISTOR REPLACEMENT FRONTSIDE CONTACT

STACKED TRANSISTOR FRONTSIDE CONTACT FORMATION

SHIFTED-CHANNEL STACKED FETS

SELECTIVELY MERGED GATES IN STACKED FETS

STACKED TRANSISTOR STRUCTURES WITH ALIGNED CELL BOUNDARIES AND SHIFTED CHANNELS

SEMICONDUCTOR DEVICE WITH LATERAL DIODES AND STACKED FETS

SEMICONDUCTOR DEVICE WITH STACKED DEVICE TYPES

LATERAL PASSIVE DIODES CO-INTEGRATED WITH NANOSHEET TECHNOLOGY

STACKED FET WITH SHIFTED CHANNEL STRUCTURE

BACKSIDE DIELECTRIC CAP

BACKSIDE CONTACT EXTENSION FOR STACKED FIELD EFFECT TRANSISTOR

STACKED TRANSISTORS HAVING DUAL WORK FUNCTION GATES

STACKED NANOSHEET DEVICES WITH INTERFACIAL LAYERS

U-SHAPED SPACER TO PROTECT THE INTRA-DEVICE SPACE REGION FOR STACKED FET

STACKED FIELD-EFFECT TRANSISTOR DEVICE WITH BACKSIDE CUT FOR TOP SOURCE/DRAIN ACCESS

ENLARGED BOTTOM CONTACT AREA IN STACKED TRANSISTORS

DUAL SIDE CUT STAGGERED STACKED FIELD EFFECT TRANSISTOR

FULL AND HALF SINGLE DIFFUSION BREAK WITH STACKED FET

DUAL SIDE STACKED TRANSISTOR

FIELD-EFFECT TRANSISTOR CRESCENT-SHAPED DIELECTRIC ISOLATION

GATE METAL JUMPER IN STACKED FET SRAM

DUAL SIDED CIRCUIT CONNECTIONS

LOCAL TRAPPED METAL CONTACT FOR STACKED FET

STACKED FET WITH BOTTOM EPI SIZE CONTROL AND WRAPAROUND BACKSIDE CONTACT

STACKED FIELD EFFECT TRANSISTORS

SHARED SOURCE/DRAIN CONTACT FOR STACKED TRANSISTORS

EXTENDED BACKSIDE CONTACT IN STACK NANOSHEET

STACKED FET WITH LOW PARASITIC-CAPACITANCE GATE

STACKED NANOSHEET FETS WITH GATE DIELECTRIC FILL

STATIC RANDOM ACCESS MEMORY DEVICE WITH STACKED FETS

MULTIPLE GATE DIELECTRICS FOR MONOLITHIC STACKED DEVICES

PROTECTION DIODE FOR STACKED FIELD EFFECT TRANSISTOR

MERGED SELF-ALIGNED BACKSIDE CONTACT

CONTACT RESISTANCE TEST STRUCTURE FOR STACKED FETS

HYBRID ORIENTATION CHANNELS AND MIXED ORIENTATION BOTTOM EPITAXY

PLACEHOLDER PROFILE FORMATION FOR BACKSIDE CONTACT

STACKED DEVICES CONTAINING AT LEAST ONE LATERAL DIODE

BACKSIDE CONTACTS FOR SOURCE/DRAIN REGIONS

ASYMMETRIC GATE EXTENSION IN STACKED FET

AIR POCKET BETWEEN TOP AND BOTTOM SOURCE/DRAIN REGIONS

FRONTSIDE TO BACKSIDE SIGNAL VIA IN EDGE CELL

DIELECTRIC SEPARATION FOR BACKSIDE POWER RAIL LINES

POWER TAP CELL FOR FRONT SIDE POWER RAIL CONNECTION TO BSPDN

Gate Dielectric for Bonded Stacked Transistors

VERTICAL TRANSISTOR WITH REDUCED CELL HEIGHT

VERTICAL TRANSISTOR WITH REDUCED CELL HEIGHT

LATCH CROSS COUPLE FOR STACKED AND STEPPED FET

Stacked Layer Memory Suitable for SRAM and Having a Long Cell.

FORKSHEET FIELD EFFECT TRANSISTOR INCLUDING SELF-ALIGNED GATE

BACKSIDE PROGRAMMABLE MEMORY

BACKSIDE PROGRAMMABLE GATE ARRAY

STACKED FET WITH EXTREMELY SMALL CELL HEIGHT

BACKSIDE MRAM WITH FRONTSIDE DEVICES

VERTICAL-TRANSPORT FIELD-EFFECT TRANSISTORS WITH SHARED BACKSIDE POWER SUPPLY

MULTI-VT SOLUTION FOR REPLACEMENT METAL GATE BONDED STACKED FET

PROTECTION DIODE TO PREVENT CHARGE DAMAGE DURING MOL

FIELD EFFECT TRANSISTOR WITH CHANNEL CAPPING LAYER

STACKED RANDOM-ACCESS-MEMORY WITH COMPLEMENTARY ADJACENT CELLS

FULL WRAP AROUND BACKSIDE CONTACT

SRAM WITH STAGGERED STACKED FET

STAGGERED PITCH STACKED VERTICAL TRANSPORT FIELD-EFFECT TRANSISTORS

FINFET DEVICES

Three-dimensional, monolithically stacked field effect transistors formed on the front and backside of a wafer

STACKED FIELD EFFECT TRANSISTOR CONTACTS

STACKED FET SRAM

MULTI-Vt REPLACEMENT METAL GATE BONDED STACKED FETs

CO-INTEGRATION OF GATE-ALL-AROUND NANOSHEET LOGIC DEVICE AND PRECISION MOL RESISTOR

SELF-ALIGNED BACKSIDE CONNECTIONS FOR TRANSISTORS

COMMON SELF ALIGNED GATE CONTACT FOR STACKED TRANSISTOR STRUCTURES

SUBTRACTIVE SOURCE DRAIN CONTACT FOR STACKED DEVICES

SEMICONDUCTOR DEVICE WITH POWER VIA

ENHANCED POWER AND SIGNAL FOR STACKED-FETS

SELF-ALIGNED BACKSIDE CONTACT WITH INCREASED CONTACT AREA

OFFSET POWER RAIL

METHOD AND STRUCTURE OF FORMING CONTACTS AND GATES FOR STAGGERED FET

METHOD AND STRUCTURE OF FORMING INDEPENDENT CONTACT FOR STAGGERED CFET

Semiconductor device having a backside power rail

BULK SUBSTRATE BACKSIDE POWER RAIL

SELF-ALIGNED BACKSIDE CONTACT WITH INCREASED CONTACT AREA

SHALLOW AND DEEP CONTACTS WITH STITCHING