Michael Mantor

METHODS TO ENABLE VARIABLE-WIDTH PACKET FETCH IN COMMAND PROCESSORS

CONFIGURABLE MULTIPLE-DIE GRAPHICS PROCESSING UNIT

LOCAL LAUNCH IN WORKGROUP PROCESSORS

RECONFIGURABLE VIRTUAL GRAPHICS AND COMPUTE PROCESSOR PIPELINE

MULTI-FORMAT OPERAND CIRCUIT

FLOATING POINT BIAS SWITCHING

STOCHASTIC ROUNDING CIRCUIT

FLOATING-POINT CONVERSION CIRCUIT

ACCELERATION UNIT WITH MODULAR ARCHITECTURE

MULTIMODAL PERSONA CONFIGURATION FOR NON-PLAYABLE CHARACTERS

HIERARCHICAL WORK SCHEDULING

STREAMING WAVE COALESCER CIRCUIT

MULTIMODAL CONTEXTUALIZER FOR NON-PLAYER CHARACTER GENERATION AND CONFIGURATION

ADAPTIVE MULTIMODAL FUSING FOR NON-PLAYER CHARACTER GENERATION AND CONFIGURATION

FUSED MULTIMODAL FRAMEWORK FOR NON-PLAYER CHARACTER GENERATION AND CONFIGURATION

CONFIGURABLE MULTIPLE-DIE GRAPHICS PROCESSING UNIT

ACCELERATED DRAW INDIRECT FETCHING

Dual vector arithmetic logic unit

Processing unit with small footprint arithmetic logic unit

HYBRID RENDER WITH DEFERRED PRIMITIVE BATCH BINNING

Hierarchical work scheduling

MATRIX MULTIPLICATION UNIT WITH FLEXIBLE PRECISION OPERATIONS

CREATING INTERCONNECTS BETWEEN DIES USING A CROSS-OVER DIE AND THROUGH-DIE VIAS

VERTICAL AND HORIZONTAL BROADCAST OF SHARED OPERANDS

ACCELERATION STRUCTURES WITH DELTA INSTANCES

CONVOLUTIONAL NEURAL NETWORK OPERATIONS

Prefetch kernels on data-parallel processors

DIE STACKING FOR MODULAR PARALLEL PROCESSORS

Hybrid render with deferred primitive batch binning

Access log and address translation log for a processor

Spatial partitioning in a multi-tenancy graphics processing unit

Sparse matrix-vector multiplication

Broadcast synchronization for dynamically adaptable arrays

Dual vector arithmetic logic unit

Dynamically adaptable arrays for vector and matrix operations

Vertical and horizontal broadcast of shared operands

Creating interconnects between dies using a cross-over die and through-die vias

Processing unit with small footprint arithmetic logic unit

Broadcast synchronization for dynamically adaptable arrays

Spatial partitioning in a multi-tenancy graphics processing unit

Hybrid render with preferred primitive batch binning and sorting

Workload-based clock adjustment at a processing unit

Dedicated vector sub-processor system

System and method for protecting GPU memory instructions against faults

COLLAPSING BUBBLES IN A PROCESSING UNIT PIPELINE

Exception handler for sampling draw dispatch identifiers

Matrix multiplication unit with flexible precision operations

Selectively dispatching waves based on accumulators holding behavioral characteristics of waves currently executing

Reconfigurable virtual graphics and compute processor pipeline

Graphics context bouncing

Pipeline including separate hardware data paths for different instruction types

Processing unit with mixed precision operations

Prefetch kernels on data-parallel processors

Split frame rendering

SOFTWARE-CONTROLLED VARIABLE WAVEFRONT SIZE EXECUTION AT GPU

System and method for protecting GPU memory instructions against faults

Primitive level preemption using discrete non-real-time and real time pipelines

Precise suspend and resume of workloads in a processing unit

Selective prefetching in multithreaded processing units

Wave creation control with dynamic resource allocation

Hybrid render with deferred primitive batch binning

Primitive level preemption using discrete non-real-time and real time pipelines

BIN STREAMOUT PREEMPTION IN A GRAPHICS PROCESSING PIPELINE

Policies for shader resource allocation in a shader core

Memory protection in highly parallel computing hardware

Single pass flexible screen/scale rasterization

Split frame rendering

STEREO RENDERING

Removing or identifying overlapping fragments after z-culling

SUPER SINGLE INSTRUCTION MULTIPLE DATA (SUPER-SIMD) FOR GRAPHICS PROCESSING UNIT (GPU) COMPUTING

Reconfigurable virtual graphics and compute processor pipeline

Pipeline including separate hardware data paths for different instruction types

Pairing SIMD lanes to perform double precision operations

Primitive shader

System and method for protecting GPU memory instructions against faults

SYSTEM AND METHOD FOR USING VIRTUAL VECTOR REGISTER FILES

Method and processing apparatus for gating redundant threads

Preemptive context switching of processes on an accelerated processing device (APD) based on time quanta

Hybrid render with preferred primitive batch binning and sorting

PROVIDING ASYNCHRONOUS DISPLAY SHADER FUNCTIONALITY ON A SHARED SHADER CORE

Graphics processing hardware for using compute shaders as front end for vertex shaders

Hybrid render with deferred primitive batch binning

Optimized Context Switching for Long-Running Processes

Prefetch kernels on a graphics processing unit

Method for urgency-based preemption of a process

Method and system for synchronization of workitems with divergent control flow

Ordering thread wavefronts instruction operations based on wavefront priority, operation counter, and ordering scheme

Hardware managed allocation and deallocation evaluation circuit

Multithreaded computing

Method for resuming an APD wavefront in which a subset of elements have faulted

Software mechanisms for managing task scheduling on an accelerated processing device (APD)

Saving and Restoring Shader Context State

Policies for Shader Resource Allocation in a Shader Core

Syscall mechanism for processor to processor calls

Partitioning resources of a processor

Handling Virtual-to-Physical Address Translation Failures

Method and Apparatus for Accommodating Multiple, Concurrent Work Inputs

Method and Apparatus for Servicing Page Fault Exceptions

Saving and Restoring Non-Shader State Using a Command Processor

Method and system for workitem synchronization