Mark A. Horowitz

MEMORY CONTROLLER WITH ERROR DETECTION AND RETRY MODES OF OPERATION

SOLID-STATE DRIVE WITH THERMAL ANNEAL FUNCTION

Memory controller with error detection and retry modes of operation

PARTIAL RESPONSE RECEIVER

Self-annealing data storage system

High speed signaling system with adaptive transmit pre-emphasis

Partial response receiver

High speed signaling system with adaptive transmit pre-emphasis

Memory controller with error detection and retry modes of operation

High speed signaling system with adaptive transmit pre-emphasis

Partial response receiver

Flash controller to provide a value that represents a parameter to a flash memory

Memory controller with error detection and retry modes of operation

Technique for determining performance characteristics of electronic devices and systems

Partial response receiver

FLASH CONTROLLER TO PROVIDE A VALUE THAT REPRESENTS A PARAMETER TO A FLASH MEMORY

Flash memory controller with calibrated data communication

High speed signaling system with adaptive transmit pre-emphasis

Multi-PAM output driver with distortion compensation

Technique for determining performance characteristics of electronic devices and systems

Flash controller to provide a value that represents a parameter to a flash memory

Memory controller that calibrates a transmit timing offset

Clock and data recovery using receiver clock spread spectrum modulation and offset compensation

Partial response receiver

High speed signaling system with adaptive transmit pre-emphasis

Dynamic memory rank configuration

Light-field microscopy with phase masking

Flash controller to provide a value that represents a parameter to a flash memory

Flash memory controller with calibrated data communication

Memory controller with error detection and retry modes of operation

Memory chip with error detection and retry modes of operation

Memory system with error detection and retry modes of operation

Controller device for use with electrically erasable programmable memory chip with error detection and retry modes of operation

Variable imaging arrangements and methods therefor

Partial response receiver

Clock and data recovery using receiver clock spread spectrum modulation and offset compensation

High speed signaling system with adaptive transmit pre-emphasis

Chip storing a value that represents adjustment to output drive strength

Chip having register to store value that represents adjustment to output drive strength

Chip having port to receive value that represents adjustment to output driver parameter

Chip having port to receive value that represents adjustment to transmission parameter

Memory system with calibrated data communication

Imaging arrangements and methods therefor

Imaging arrangements and methods therefor

Chip having register to store value that represents adjustment to reference voltage

Multiphase receiver with equalization circuitry

Thermal anneal using word-line heating element

Memory controller with circuitry to set memory device-specific reference voltages

Variable imaging arrangements and methods therefor

Technique for determining performance characteristics of electronic devices and systems

Imaging arrangements and methods therefor

Imaging arrangements and methods therefor

High speed signaling system with adaptive transmit pre-emphasis

High speed signaling system with adaptive transmit pre-emphasis

Chip having register to store value that represents adjustment to reference voltage

Imaging arrangements and methods therefor

THERMAL ANNEAL USING WORD-LINE HEATING ELEMENT

Memory system with error detection and retry modes of operation

Clock and data recovery using receiver clock spread spectrum modulation and offset compensation

Variable imaging arrangements and methods therefor

Multiphase receiver with equalization circuitry

Variable imaging arrangements and methods therefor

High speed signaling system with adaptive transmit pre-emphasis

Chip having register to store value that represents adjustment to reference voltage

Correction of optical abberations

Equalizing receiver

Partial response receiver

Memory system with calibrated data communication

Technique for determining performance characteristics of electronic devices and systems

Imaging arrangements and methods therefor

Imaging arrangements and methods therefor

Integrated circuit heating to effect in-situ annealing

Memory controller and method utilizing equalization co-efficient setting

Linear Transformation Circuit

Integrating receiver with precharge circuitry

Memory system with error detection and retry modes of operation

Method and apparatus for determining a calibration signal

Partial response receiver

Multiphase receiver with equalization

High speed signaling system with adaptive transmit pre-emphasis

Clock and data recovery employing piece-wise estimation on the derivative of the frequency

Method and apparatus for transmitting data with reduced coupling noise

Variable imaging arrangements and methods therefor

Noise Model Method of Predicting Mismatch Effects on Transient Circuit Behaviors

Memory system with calibrated data communication

Partial response receiver

System and dynamic random access memory device having a receiver

Technique for determining performance characteristics of electronic devices and systems

Partial response receiver

Adaptive optical signal processing with multimode waveguides

Correction of optical aberrations

High speed signaling system with adaptive transmit pre-emphasis

Microscopy arrangements and approaches

Partial response receiver

Integrated circuit device and signaling method with phase control based on information in external memory device

Adaptive optical signal processing with multimode waveguides

Integrated circuit memory device and signaling method for adjusting drive strength based on topography of integrated circuit devices

Integrated circuit device and signaling method with topographic dependent equalization coefficient

Adaptive optical signal processing with multimode waveguides

Noise-tolerant signaling schemes supporting simplified timing and data recovery