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Inventor profile of:

Bruce MILLAR

City:

Stittsville

Country:

Canada

Published Applications:

Last publication date:

2020-08-20

Top Assignees for applications by Bruce MILLAR

The entities that hold a legal rights for patent applications filed by inventor MILLAR Bruce:

MOSAID TECHNOLOGIES INCORPORATED 10 Kanata, Canada
Mosaid Technologies Incorporated 10 Ottawa, Ontario, Canada
MOSAID TECHNOLOGIES INCORPORATED 10 OTTAWA, Canada
Conversant Intellectual Property Management Inc. 5 Ottawa, Canada
MOSAID Technologies Incorporated 4 Kanata, Ontario, Canada
MOSAID Technologies Incorporated 1 Ottawa, Ontario, -

Recent patent applications by MILLAR Bruce

Bruce MILLAR from Stittsville, CA has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2020-08-20

US20200266818A1

Electricity

Dynamic impedance control for input/output buffers

#2 | 2018-12-20

US20180367140A9

Electricity

Dynamic impedance control for input/output buffers

#3 | 2018-09-13

US20180262195A1

Electricity

DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS

#4 | 2016-09-22

US20160277027A1

Electricity

DYNAMIC IMPEDANCE CONTROL FOR INPUT/OUTPUT BUFFERS

#5 | 2015-03-19

US20150078057A1

Physics

HIGH BANDWIDTH MEMORY INTERFACE

#6 | 2015-01-08

US20150008956A1

Electricity

Dynamic impedance control for input/output buffers

#7 | 2014-03-13

US20140071781A1

Physics

VOLTAGE DOWN CONVERTER FOR HIGH SPEED MEMORY

#8 | 2013-12-12

US20130329482A1

Physics

HIGH BANDWIDTH MEMORY INTERFACE

#9 | 2013-05-23

US20130132761A1

Physics

High bandwidth memory interface

#10 | 2012-07-12

US20120176118A1

Physics

Voltage down converter for high speed memory

#11 | 2012-01-26

US20120019282A1

Electricity

Dynamic impedance control for input/output buffers

#12 | 2011-03-17

US20110063006A1

Electricity

Timing vernier using a delay locked loop

#13 | 2011-02-24

US20110043246A1

Electricity

Dynamic impedance control for input/output buffers

#14 | 2010-10-21

US20100268906A1

Physics

HIGH BANDWIDTH MEMORY INTERFACE

#15 | 2010-05-13

US20100117698A1

Electricity

Timing vernier using a delay locked loop

#16 | 2010-04-22

US20100097869A1

Physics

Memory system having incorrupted strobe signals

#17 | 2009-01-22

US20090021998A1

Physics

Memory system having incorrupted strobe signals

#18 | 2008-12-11

US20080303546A1

Electricity

Dynamic impedance control for input/output buffers

#19 | 2008-10-16

US20080252344A1

Electricity

Timing vernier using a delay locked loop

#20 | 2008-10-02

US20080238534A1

Electricity

Phase shifting in DLL/PLL

#21 | 2008-08-07

US20080186790A1

Physics

Voltage down converter for high speed memory

#22 | 2008-05-22

US20080120458A1

Physics

High bandwidth memory interface

#23 | 2008-05-22

US20080120457A1

Physics

Apparatuses for synchronous transfer of information

#24 | 2008-03-13

US20080065820A1

Physics

High bandwidth memory interface

#25 | 2007-07-05

US20070157144A1

Physics

ASIC design using clock and power grid standard cell

#26 | 2007-03-22

US20070063750A1

Electricity

Timing vernier using a delay locked loop

#27 | 2007-02-08

US20070030749A1

Physics

Voltage down converter for high speed memory

#28 | 2006-01-26

US20060017484A1

Electricity

Timing vernier using a delay locked loop

#29 | 2005-06-09

US20050122144A1

Electricity

Timing vernier using a delay locked loop

#30 | 2005-04-14

US20050081012A1

Physics

High bandwidth memory interface

#31 | 2005-02-08

US10402130

Timing vernier using a delay locked loop

InventorID:

267249 ⎘