Inventor profile of:

Steven Scheer

City:

Austin, Texas

Country:

United States

Published Applications:

22

Last publication date:

2013-10-31

Top Assignees for applications by Steven Scheer

The entities that hold a legal rights for patent applications filed by inventor Scheer Steven:

Recent patent applications by Scheer Steven

Steven Scheer from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2013-10-31
US20130288487A1
Electricity

Method and system for controlling a spike anneal process

#2 | 2012-09-27
US20120244645A1
Electricity

Electrostatic post exposure bake apparatus and method

#3 | 2012-02-23
US20120045722A1
Physics

TECHNIQUE TO FORM A SELF-ALIGNED DOUBLE PATTERN

#4 | 2012-02-23
US20120045721A1
Physics

METHOD FOR FORMING A SELF-ALIGNED DOUBLE PATTERN

#5 | 2011-11-03
US20110269078A1
Physics

Substrate treatment to reduce pattern roughness

#6 | 2011-08-25
US20110205505A1
Physics

Line pattern collapse mitigation through gap-fill material application

#7 | 2010-10-28
US20100273111A1
Physics

Dual tone development with plural photo-acid generators in lithographic applications

#8 | 2010-10-28
US20100273107A1
Physics

Dual tone development with a photo-activated acid enhancement component in lithographic applications

#9 | 2010-10-28
US20100273099A1
Physics

Flood exposure process for dual tone development in lithographic applications

#10 | 2010-09-30
US20100248152A1
Electricity

Using electric-field directed post-exposure bake for double-patterning (D-P)

#11 | 2010-05-13
US20100119960A1
Physics

Dual tone development processes

#12 | 2010-03-25
US20100075238A1
Physics

Variable resist protecting groups

#13 | 2010-03-18
US20100068654A1
Physics

Method for creating gray-scale features for dual tone development processes

#14 | 2010-03-04
US20100055625A1
Physics

Method of process optimization for dual tone development

#15 | 2010-03-04
US20100055624A1
Physics

METHOD OF PATTERNING A SUBSTRATE USING DUAL TONE DEVELOPMENT

#16 | 2009-09-03
US20090220893A1
Electricity

Method for patterning a semiconductor wafer

#17 | 2009-06-04
US20090144691A1
Electricity

Enhanced process yield using a hot-spot library

#18 | 2008-10-02
US20080241400A1
Physics

VACUUM ASSIST METHOD AND SYSTEM FOR REDUCING INTERMIXING OF LITHOGRAPHY LAYERS

#19 | 2008-10-02
US20080237214A1
Mechanical engineering

Methods and heat treatment apparatus for uniformly heating a substrate during a bake process

#20 | 2008-04-03
US20080079934A1
Physics

Method of real time dynamic CD control

#21 | 2007-10-25
US20070250200A1
Physics

Optimized characterization of wafers structures for optical metrology

#22 | 2007-09-27
US20070226674A1
Physics

System and method for semiconductor device fabrication using modeling

InventorID:

3104719 ⎘