Inventor profile of:

Paul Demone

City:

Kanata

Country:

Canada

Published Applications:

21

Last publication date:

2026-03-26

Top Assignees for applications by Paul Demone

The entities that hold a legal rights for patent applications filed by inventor Demone Paul:

Recent patent applications by Demone Paul

Paul Demone from Kanata, CA has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2026-03-26
US20260088724A1
Electricity

CONTROL OF A RESONANT CONVERTER USING SWITCH PATHS DURING POWER-UP

#2 | 2023-01-12
US20230010711A1
Electricity

CONTROL OF A RESONANT CONVERTER USING SWITCH PATHS DURING POWER-UP

#3 | 2012-12-13
US20120314457A1
Electricity

Control arrangement for a resonant mode power converter

#4 | 2012-11-01
US20120274298A1
Electricity

Power factor correction converter control offset

#5 | 2012-04-19
US20120091982A1
Electricity

Power factor correction converter control offset

#6 | 2012-03-08
US20120057372A1
Electricity

Control arrangement for a resonant mode power converter

#7 | 2011-02-24
US20110044074A1
Electricity

Control arrangement for a resonant mode power converter

#8 | 2010-09-16
US20100232237A1
Physics

High speed DRAM architecture with uniform access latency

#9 | 2010-06-03
US20100135089A1
Physics

Method and apparatus for synchronization of row and column access operations

#10 | 2009-12-24
US20090316454A1
Electricity

Power factor correction converter control offset

#11 | 2009-05-28
US20090135664A1
Physics

Method and apparatus for synchronization of row and column access operations

#12 | 2009-02-05
US20090034347A1
Physics

High speed DRAM architecture with uniform access latency

#13 | 2008-08-21
US20080198638A1
Electricity

Control arrangement for a resonant mode power converter

#14 | 2007-12-13
US20070286000A1
Physics

Method and apparatus for synchronization of row and column access operations

#15 | 2007-09-11
US10337346
-

Method and apparatus for simultaneous differential data sensing and capture in a high speed memory

#16 | 2006-07-06
US20060146641A1
Physics

High speed DRAM architecture with uniform access latency

#17 | 2006-04-20
US20060083083A1
Physics

Method and apparatus for synchronization of row and column access operations

#18 | 2005-08-18
US20050180246A1
Physics

High speed DRAM architecture with uniform access latency

#19 | 2005-05-10
US10804182
-

High speed DRAM architecture with uniform access latency

#20 | 2005-03-29
US10337972
-

Method and apparatus for synchronization of row and column access operations

#21 | 2005-02-17
US20050036386A1
Physics

Method and apparatus for synchronization of row and column access operations

InventorID:

3114696 ⎘