Peter Gregorius

Semiconductor memory with memory cell portions having different access speeds

Distributed command and address bus architecture for a memory module having portions of bus lines separately disposed

Method and system including plural memory controllers and a memory access control bus for accessing a memory device

Multi-port DRAM architecture for accessing different memory partitions

Horizontal dual in-line memory modules

Memory circuit

Method and apparatus for determining a skew

Current mode digital data transmitter

Method For Processing Data in a Memory Arrangement, Memory Arrangement and Computer System

Method for reconstructing data clocked at a symbol rate from a distorted analog signal

Method and apparatus for phase detection

Memory arrangement having efficient arrangement of devices

Memory module device

Timing recovery phase locked loop

Data transfer in a memory device

Memory module and memory device and method of operating a memory device

Generating a sampling clock signal in a communication block of a memory device

Method of transferring signals between a memory device and a memory controller

DB-linear variable gain amplifier (VGA) stage with a high broad band

Semiconductor memory system and memory module

Semiconductor memory chip

High-speed interface circuit for semiconductor memory chips and memory system including the same

Phase locked loop having reduced inherent noise

Semiconductor memory system and semiconductor memory chip

Method for sampling phase control

Method of operating a memory device, memory module, and a memory device comprising the memory module

Semiconductor memory chip and memory system

Re-driving CAwD and rD signal lines

Memory system and method of accessing memory chips of a memory system

Control unit for deactivating and activating the control signals

Synchronization and data recovery device

Method of reconstructing data transmitted over a transmission path in a receiver and corresponding device

Memory device having components for transmitting and receiving signals synchronously

Synchronous parallel/serial converter

Integrated memory device and memory module

Semiconductor memory system and method for the transfer of write and read data signals in a semiconductor memory system

Semiconductor memory chip, semiconductor memory module and method for transmitting write data to semiconductor memory chips

Memory system with two clock lines and a memory device

Memory device, memory controller and memory system having bidirectional clock lines

Method and device for generating a clock signal using a phase difference signal and a feedback signal

Code driver for a memory controller

Memory controller with a plurality of parallel transfer blocks

Device for the regulated delay of a clock signal

Device for setting a clock delay

Cell array with mismatch reduction

Method and filter arrangement for digital recursive filtering in the time domain

Device for the production of standard-compliant signals