QIMONDA AG

Memory-module controller, memory controller and corresponding memory arrangement and also method for error correction

Method for fabricating an integrated circuit including resistivity changing material having a planarized surface

Distributed command and address bus architecture for a memory module having portions of bus lines separately disposed

System and method for packaged memory

Multi-mode bus inversion method and apparatus

Method and apparatus for reducing charge trapping in high-k dielectric material

Memory device with multiple capacitor types

Integrated circuit including selectable address and data multiplexing mode

Bus termination system and method

Word line to bit line spacing method and apparatus

Method of forming an integrated circuit with NAND flash array segments and intra array multiplexers and corresponding integrated circuit with NAND flash array segments and intra array multiplexers

System and method of correcting errors in SEM-measurements

Method and integrated circuit for determining the state of a resistivity changing memory cell

System including preemphasis driver circuit and method

Integrated circuit with floating-gate electrodes including a transition metal and corresponding manufacturing method

Semiconductor device with an interconnect element and method for manufacture

Memory including periphery circuitry to support a portion or all of the multiple banks of memory cells

Reduced-stress through-chip feature and method of making the same

Method of double patterning, method of processing a plurality of semiconductor wafers and semiconductor device

Electrode of an integrated circuit

Method for structuring a substrate using a metal mask layer formed using a galvanization process

Method and device for redundancy replacement in semiconductor devices using a multiplexer

Integrated circuit including diode memory cells

Memory circuit

Method and apparatus for determining a skew

Memory-module controller, memory controller and corresponding memory arrangement, and also method for error correction

Integrated circuit device for receiving differential and single-ended signals

Integrated circuit including vertical diode

Semiconductor memory arrangement

Integrated circuit memory device responsive to word line/bit line short-circuit

Apparatus and method for determining trench parameters

Test method, integrated circuit and test system

Integrated circuit device having openings in a layered structure

Minority carrier sink for a memory cell array comprising nonvolatile semiconductor memory cells

Memory module with ranks of memory chips

Semiconductor memory device with temperature control

Reduced-delay clocked logic

Integrated circuit and methods of manufacturing a contact arrangement and an interconnection arrangement

Power savings for memory with error correction mode

Integrated semiconductor memory and method for operating a data path in a semiconductor memory

Solder pillar bumping and a method of making the same

Memory apparatus with a bus architecture

Electrical through contact

Method of removing refractory metal layers and of siliciding contact areas

Method for applying solder to redistribution lines

Integrated semiconductor memory device with clock generation

System and method for projecting a pattern from a mask onto a substrate

Memory circuit having memory chips parallel connected to ports and corresponding production method

Memory arrangement

Memory arrangement having efficient arrangement of devices

Method for producing a mask for the lithographic projection of a pattern onto a substrate

Integrated semiconductor memory devices with generation of voltages

Method for searching for potential faults in a layout of an integrated circuit

Semiconductor memory component with body region of memory cell having a depression and a graded dopant concentration