Peter Gregorius

Semiconductor memory with memory cell portions having different access speeds

Stacking Technique for Circuit Devices

Memory device and memory system comprising a memory device and a memory control device

High speed memory architecture

Bus termination system and method

Circuit with selectable data paths

METHOD FOR CONTROLLING A MEMORY MODULE AND MEMORY CONTROL UNIT

Interface voltage adjustment based on error detection

Integrated Circuit with Improved Data Rate

Integrated circuit with wireless connection

DRAM with Page Access

MEMORY DEVICE, METHOD FOR ACCESSING A MEMORY DEVICE AND METHOD FOR ITS MANUFACTURING

Method and apparatus for storage device with a logic unit and method for manufacturing same

Multi-die memory, apparatus and multi-die memory stack

Memory system with extended memory density capability

Memory circuit

Method and apparatus for determining a skew

METHOD AND APPARATUS FOR MONITORING A MEMORY DEVICE

Data conversion

Clock and data recovery unit

Method and device for transmitting outgoing useful signals and an outgoing clock signal

Training connections in a memory arrangement

Memory device, memory system and method of operating such

Data receiver with clock recovery circuit

Feed forward clock and data recovery unit

Feed forward equalizer and a method for analog equalization of a data signal

Memory device and method of operating such

Semiconductor memory chip

Method of transmitting data between different clock domains

Memory arrangement having efficient arrangement of devices

Data handover unit for transferring data between different clock domains by parallelly reading out data bits from a plurality of storage elements

Apparatus and method for avoiding steady-state oscillations in the generation of clock signals

Semiconductor memory chip

Circuit arrangement for recovering clock and data from a received signal

Semiconductor memory chip and memory system

Synchronous signal generator

Memory system and method of accessing memory chips of a memory system

Method for measuring the delay time of a signal line

High-speed interface circuit for semiconductor memory chips and memory system including semiconductor memory chips

Line driver for digital signal transmission

Device for the recovery of data from a received data signal

Synchronous parallel/serial converter

Memory module with a clock signal regeneration circuit and a register circuit for temporarily storing the incoming command and address signals

Method and device for estimating channel properties of a transmission channel

Device for reconstructing data from a received data signal and corresponding transceiver

Line driver for transmitting data