Inventor profile of:

Hermann Ruckerbauer

City:

Moos

Country:

Germany

Published Applications:

84

Last publication date:

2011-02-10

Top Assignees for applications by Hermann Ruckerbauer

The entities that hold a legal rights for patent applications filed by inventor Ruckerbauer Hermann:

Recent patent applications by Ruckerbauer Hermann

Hermann Ruckerbauer from Moos, DE has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2011-02-10
US20110034045A1
Electricity

Stacking Technique for Circuit Devices

#2 | 2010-04-01
US20100082871A1
Physics

Distributed command and address bus architecture for a memory module having portions of bus lines separately disposed

#3 | 2010-03-25
US20100077157A1
Physics

Method and system including plural memory controllers and a memory access control bus for accessing a memory device

#4 | 2010-03-25
US20100077139A1
Physics

Multi-port DRAM architecture for accessing different memory partitions

#5 | 2010-03-25
US20100074038A1
Physics

Memory dies for flexible use and method for configuring memory dies

#6 | 2010-03-11
US20100062621A1
Electricity

Horizontal dual in-line memory modules

#7 | 2010-02-25
US20100046266A1
Physics

High speed memory architecture

#8 | 2010-02-25
US20100044877A1
Electricity

Electronic device having a chip stack

#9 | 2010-02-11
US20100032820A1
Electricity

Stacked Memory Module

#10 | 2010-02-04
US20100030934A1
Physics

Bus termination system and method

#11 | 2009-11-19
US20090287957A1
Physics

METHOD FOR CONTROLLING A MEMORY MODULE AND MEMORY CONTROL UNIT

#12 | 2009-10-29
US20090268539A1
Physics

Chip, multi-chip system in a method for performing a refresh of a memory array

#13 | 2009-10-29
US20090267678A1
Electricity

Integrated Circuit with Improved Data Rate

#14 | 2009-10-29
US20090267084A1
Electricity

Integrated circuit with wireless connection

#15 | 2009-09-03
US20090219063A1
Physics

Methods and articles of manufacture for operating electronic devices on a plurality of clock signals

#16 | 2009-07-30
US20090190432A1
Physics

DRAM with Page Access

#17 | 2009-07-09
US20090175115A1
Physics

MEMORY DEVICE, METHOD FOR ACCESSING A MEMORY DEVICE AND METHOD FOR ITS MANUFACTURING

#18 | 2009-07-09
US20090175100A1
Physics

Method and apparatus for storage device with a logic unit and method for manufacturing same

#19 | 2009-06-25
US20090161401A1
Physics

Multi-die memory, apparatus and multi-die memory stack

#20 | 2009-06-11
US20090150710A1
Physics

Memory system with extended memory density capability

#21 | 2009-06-04
US20090144583A1
Physics

Memory circuit

#22 | 2009-06-04
US20090141843A1
Electricity

Method and apparatus for determining a skew

#23 | 2009-06-04
US20090141576A1
Physics

Method of refreshing data in a storage location based on heat dissipation level and system thereof

#24 | 2009-05-21
US20090129189A1
Physics

METHOD AND APPARATUS FOR MONITORING A MEMORY DEVICE

#25 | 2009-02-19
US20090046534A1
Physics

Method of operating a memory apparatus, memory device and memory apparatus

#26 | 2009-02-12
US20090040861A1
Physics

Method of operating a memory apparatus, memory device and memory apparatus

#27 | 2009-02-12
US20090039915A1
Physics

Integrated circuit, chip stack and data processing system

#28 | 2009-01-13
US10831001
-

Input receiver circuit

#29 | 2008-12-04
US20080301370A1
Physics

Memory Module

#30 | 2008-11-04
US10792408
-

Buffer chip and method for controlling one or more memory arrangements

#31 | 2008-10-02
US20080237891A1
Electricity

Semiconductor device

#32 | 2008-01-24
US20080022037A1
Physics

Memory system and method for transferring data therein

#33 | 2007-11-15
US20070263425A1
Physics

MEMORY ARRANGEMENT

#34 | 2007-10-25
US20070246257A1
Electricity

Memory circuit having memory chips parallel connected to ports and corresponding production method

#35 | 2007-10-04
US20070228436A1
Electricity

Arrangement of semiconductor memory devices and semiconductor memory module comprising an arrangement of semiconductor memory devices

#36 | 2007-09-25
US10724135
-

Memory module and method for operating a memory module in a data memory system

#37 | 2007-08-23
US20070195505A1
Electricity

Memory module device

#38 | 2007-08-23
US20070194447A1
Electricity

Semiconductor component comprising an integrated semiconductor chip and a chip housing, and electronic device

#39 | 2007-08-23
US20070194446A1
Electricity

Memory module comprising an electronic printed circuit board and a plurality of semiconductor components and method

#40 | 2007-06-28
US20070150792A1
Physics

Memory module comprising a plurality of memory devices

#41 | 2007-05-22
US10133795
-

Method for repairing hardware faults in memory chips

#42 | 2007-05-03
US20070096333A1
Electricity

Optimal stacked die organization

#43 | 2007-04-05
US20070079085A1
Physics

Apparatus for storing memory words

#44 | 2007-04-05
US20070079057A1
Physics

Semiconductor memory system and memory module

#45 | 2007-03-29
US20070073942A1
Physics

High-speed interface circuit for semiconductor memory chips and memory system including the same

#46 | 2007-03-15
US20070058409A1
Physics

Semiconductor memory arrangement with branched control and address bus

#47 | 2007-03-15
US20070058408A1
Physics

Semiconductor memory array with serial control/address bus

#48 | 2007-03-15
US20070057695A1
Physics

Semiconductor memory chip with re-drive unit for electrical signals

#49 | 2007-02-08
US20070033489A1
Physics

Semiconductor Memory Device and Method of Operating the Same

#50 | 2007-02-08
US20070033487A1
Physics

Semiconductor memory device including a signal control device and method of operating the same

#51 | 2007-02-08
US20070033351A1
Physics

Semiconductor memory module unit for point-to-point data interchange

#52 | 2007-02-01
US20070028146A1
Physics

Semiconductor memory device system, and method for operating a semiconductor memory device system

#53 | 2007-02-01
US20070025131A1
Physics

Re-driving CAwD and rD signal lines

#54 | 2007-01-11
US20070011574A1
Physics

Memory device with error correction code module

#55 | 2006-12-28
US20060291263A1
Physics

Memory system and method of accessing memory chips of a memory system

#56 | 2006-11-23
US20060265543A1
Physics

Method for setting a second rank address from a first rank address in a memory module

#57 | 2006-11-02
US20060248260A1
Electricity

Circuit system

#58 | 2006-09-14
US20060202328A1
Physics

Memory module and memory configuration with stub-free signal lines and distributed capacitive loads

#59 | 2006-07-13
US20060155948A1
Physics

Semiconductor memory system and method for data transmission

#60 | 2006-06-15
US20060129740A1
Physics

Memory device, memory controller and method for operating the same

#61 | 2006-06-08
US20060123265A1
Physics

Memory module with a clock signal regeneration circuit and a register circuit for temporarily storing the incoming command and address signals

#62 | 2006-05-25
US20060112239A1
Physics

Memory device for use in a memory module

#63 | 2006-05-25
US20060112230A1
Physics

Integrated memory device and memory module

#64 | 2006-05-18
US20060104132A1
Physics

Semiconductor memory system and method for the transfer of write and read data signals in a semiconductor memory system

#65 | 2006-05-09
US10245629
-

Integrated circuit and method for operating the integrated circuit

#66 | 2006-05-09
US10215228
-

Method and apparatus for synchronous signal transmission between at least two logic or memory components

#67 | 2006-05-04
US20060095826A1
Physics

Semiconductor memory chip, semiconductor memory module and method for transmitting write data to semiconductor memory chips

#68 | 2006-05-04
US20060095652A1
Physics

Memory device and method for receiving instruction data

#69 | 2006-05-04
US20060092715A1
Physics

System for determining a reference level and evaluating a signal on the basis of the reference level

#70 | 2006-03-30
US20060067157A1
Physics

Memory system with two clock lines and a memory device

#71 | 2006-03-30
US20060067156A1
Physics

Memory device, memory controller and memory system having bidirectional clock lines

#72 | 2006-03-23
US20060062039A1
Physics

DQS signaling in DDR-III memory systems without preamble

#73 | 2006-03-07
US10609873
-

Method, adapter card and configuration for an installation of memory modules

#74 | 2005-10-25
US10675492
-

Method for calibrating semiconductor devices using a common calibration reference and a calibration circuit

#75 | 2005-07-19
US10609871
-

Configuration, plug-in mount and contact element for fixing and contacting switching assemblies on a substrate

#76 | 2005-05-24
US10610184
-

Zero insertion force mount for fixing and making contact with circuit subassemblies on a substrate

#77 | 2005-04-14
US20050078532A1
Physics

Semiconductor memory module

#78 | 2005-03-03
US20050047250A1
Physics

Semiconductor memory module

#79 | 2005-02-24
US20050044305A1
Physics

Semiconductor memory module

#80 | 2005-02-24
US20050041516A1
Physics

Memory system and method for transferring data therein

#81 | 2005-02-17
US20050038966A1
Physics

Memory arrangement

#82 | 2005-02-17
US20050036349A1
Physics

Semiconductor memory module

#83 | 2005-02-03
US20050024963A1
Physics

Semiconductor memory module

#84 | 2005-01-11
US10610241
-

Connector for a plurality of switching assemblies with compatible interfaces

InventorID:

3514577 ⎘