Jan Boris Philipp

Method for fabricating an integrated circuit including resistivity changing material having a planarized surface

Memory including vertical bipolar select device and resistive memory element

Current constricting phase change memory element structure

Phase change memory with tapered heater

Memory cell having improved mechanical stability

Integrated circuit including force-filled resistivity changing material

Current constricting phase change memory element structure

Program method with locally optimized write parameters

Conditioning operations for memory cells

Multiple write configurations for a memory cell

Integrated circuit including resistivity changing material having a planarized surface

Phase change memory with tapered heater

Memory device having drift compensated read operation and associated method

Mushroom phase change memory having a multilayer electrode

INTEGRATED CIRCUIT INCLUDING CONTACT CONTACTING BOTTOM AND SIDEWALL OF ELECTRODE

Circuit for programming a memory element

Integrated circuit including vertical diode

Integrated circuit having multilayer electrode

Integrated circuit including vertical diode

INTEGRATED CIRCUIT INCLUDING VERTICAL DIODE

Integrated circuit including logic portion and memory portion

Memory having shared storage material

MEMORY HAVING SHARED STORAGE MATERIAL

Integrated circuit including spacer defined electrode

Integrated circuit having contact including material between sidewalls

Multi-level resistive memory cell using different crystallization speeds

Memory including write circuit for providing multiple reset pulses

Circuit for programming a memory element

INTEGRATED CIRCUIT INCLUDING SPACER MATERIAL LAYER

Stacked SONOS memory

Method to prevent overreset

Method for manufacturing a phase change memory device with pillar bottom electrode

Resistive memory including buried word lines

Resistance Limited Phase Change Memory Material

Pillar phase change memory cell

Memory that limits power consumption

Spin glass memory cell

Memory cell with trigger element

Resistive memory including selective refresh operation

System that prevents reduction in data retention

Resistive memory including refresh operation

Semiconductor device including multi-bit memory cells and a temperature budget sensor

Resistive memory having shunted memory cells

Resistive memory having shunted memory cells

Integrated circuit to identify read disturb condition in memory cell

INTEGRATED CIRCUIT WITH RESISTIVITY CHANGING MATERIAL HAVING A STEP-LIKE PROGRAMMING CHARACTERISTITIC

Integrated circuit having memory having a step-like programming characteristic

Integrated circuit with memory having a step-like programming characteristic

Phase change memory cell including nanocomposite insulator

Integrated circuit having a phase change memory cell including a narrow active region width

Memory cell programmed using a temperature controlled set pulse

Integrated circuit having a precharging circuit

Phase change memory having temperature budget sensor

Transitioning the state of phase change material by annealing

Phase-change memory cell adapted to prevent over-etching or under-etching

Phase change memory

Memory having storage locations within a common volume of phase change material

Integrated circuit including sidewall spacer

Phase change memory cell with limited switchable volume

Thermal isolation of phase change memory cells

Integrated circuit having resistive memory cells

Phase change memory cell including multiple phase change material portions

Integrated circuit having an insulated memory

Phase change memory having multilayer thermal insulation

Integrated circuit having resistive memory

Integrated circuit having a switch

Integrated circuit having a switch

Low power phase change memory cell with large read signal