Inventor profile of:

Igor Peidous

City:

Fishkill, New York

Country:

United States

Published Applications:

20

Last publication date:

2010-10-07

Top Assignees for applications by Igor Peidous

The entities that hold a legal rights for patent applications filed by inventor Peidous Igor:

Recent patent applications by Peidous Igor

Igor Peidous from Fishkill, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2010-10-07
US20100252866A1
Electricity

Transistor having a channel with tensile strain and oriented along a crystallographic orientation with increased charge carrier mobility

#2 | 2010-04-22
US20100096698A1
Electricity

Stress enhanced transistor

#3 | 2010-04-01
US20100078825A1
Electricity

Method for fabricating interconnect structures for semiconductor devices

#4 | 2009-02-26
US20090050963A1
Electricity

STRESSED MOS DEVICE AND METHODS FOR ITS FABRICATION

#5 | 2009-01-29
US20090026545A1
Electricity

Integrated circuit employing variable thickness film

#6 | 2008-12-09
US11205797
-

Methods for fabricating a stressed MOS device

#7 | 2008-11-25
US11231405
-

Stressed MOS device and methods for its fabrication

#8 | 2008-10-23
US20080258175A1
Electricity

Stressed MOS device

#9 | 2008-10-02
US20080242014A1
Electricity

Methods for fabricating semiconductor substrates with silicon regions having differential crystallographic orientations

#10 | 2008-08-12
US11269241
-

Stressed MOS device and method for its fabrication

#11 | 2008-07-31
US20080182370A1
Electricity

Methods for fabricating low contact resistance CMOS circuits

#12 | 2008-06-19
US20080142835A1
Electricity

Stress enhanced transistor and methods for its fabrication

#13 | 2008-05-22
US20080119031A1
Electricity

Stress enhanced MOS transistor and methods for its fabrication

#14 | 2008-04-10
US20080083952A1
Electricity

Semiconductor structures including multiple crystallographic orientations and methods for fabrication thereof

#15 | 2008-03-25
US11207265
-

Methods for fabricating a CMOS device including silicide contacts

#16 | 2008-01-17
US20080014704A1
Electricity

Field effect transistors and methods for fabricating the same

#17 | 2007-11-01
US20070252144A1
Electricity

Transistor having a channel with tensile strain and oriented along a crystallographic orientation with increased charge carrier mobility

#18 | 2007-03-29
US20070072380A1
Electricity

Methods for fabrication of a stressed MOS device

#19 | 2007-02-08
US20070032024A1
Electricity

Methods for fabricating a stressed MOS device

#20 | 2007-02-01
US20070026599A1
Electricity

Methods for fabricating a stressed MOS device

InventorID:

3665104 ⎘