Inventor profile of:

Cecile Aulnette

City:

Grenoble

Country:

France

Published Applications:

24

Last publication date:

2009-01-22

Top Assignees for applications by Cecile Aulnette

The entities that hold a legal rights for patent applications filed by inventor Aulnette Cecile:

Recent patent applications by Aulnette Cecile

Cecile Aulnette from Grenoble, FR has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2009-01-22
US20090023267A1
Electricity

Method of reducing roughness of a thick insulating layer

#2 | 2008-06-19
US20080142844A1
Electricity

Semiconductor heterostructure

#3 | 2008-06-05
US20080132031A1
Electricity

Method of manufacturing a semiconductor heterostructure

#4 | 2007-02-01
US20070023867A1
Electricity

Film taking-off method

#5 | 2007-01-25
US20070020947A1
Electricity

Method of reducing roughness of a thick insulating layer

#6 | 2006-12-21
US20060286770A1
Electricity

Method for concurrently producing at least a pair of semiconductor structures that each include at least one useful layer on a substrate

#7 | 2006-10-03
US10686084
-

Method for concurrently producing at least a pair of semiconductor structures that each include at least one useful layer on a substrate

#8 | 2006-04-27
US20060088979A1
Electricity

Semiconductor structure for providing strained crystalline layer on insulator and method for fabricating same

#9 | 2006-04-25
US10726039
-

Recycling of a wafer comprising a buffer layer after having separated a thin layer therefrom by mechanical means

#10 | 2006-04-13
US20060076578A1
Electricity

Recycling a wafer comprising a buffer layer, after having separated a thin layer therefrom

#11 | 2006-03-28
US10614327
-

Transfer of a thin layer from a wafer comprising a buffer layer

#12 | 2006-03-07
US10764289
-

Recycling a wafer comprising a buffer layer, after having separated a thin layer therefrom

#13 | 2006-02-07
US10763978
-

Semiconductor structure for providing strained crystalline layer on insulator and method for fabricating same

#14 | 2006-01-31
US10784032
-

Method of producing a semiconductor structure having at least one support substrate and an ultrathin layer

#15 | 2005-10-18
US10704703
-

Semiconductor structure and methods for fabricating same

#16 | 2005-09-01
US20050191825A1
Electricity

Methods for transferring a thin layer from a wafer having a buffer layer

#17 | 2005-09-01
US20050189323A1
Electricity

Recycling by mechanical means of a wafer comprising a multilayer structure after taking-off a thin layer thereof

#18 | 2005-08-04
US20050170611A1
Electricity

Recycling of a wafer comprising a multi-layer structure after taking-off a thin layer

#19 | 2005-08-04
US20050167002A1
Electricity

Recycling of a wafer comprising a multi-layer structure after taking-off a thin layer

#20 | 2005-07-14
US20050150447A1
Electricity

Recycling by mechanical means of a wafer comprising a multilayer structure after taking-off a thin layer thereof

#21 | 2005-06-21
US10637078
-

Method and apparatus for adjusting the thickness of a thin layer of semiconductor material

#22 | 2005-03-31
US20050070078A1
Electricity

Indirect bonding with disappearance of bonding layer

#23 | 2005-03-31
US20050066886A1
Electricity

Method of fabrication of a substrate for an epitaxial growth

#24 | 2005-02-03
US20050023610A1
Electricity

Semiconductor-on-insulator structure having high-temperature elastic constraints

InventorID:

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