Munich
Germany
23
2009-12-17
The entities that hold a legal rights for patent applications filed by inventor Specht Michael:
Michael Specht from Munich, DE has applied for patents for these inventions. The list has both pending applications and granted patents:
Integrated circuits having a contact region and methods for manufacturing the same
#2 | 2009-03-19Integrated circuit including a first gate stack and a second gate stack and a method of manufacturing
#3 | 2008-12-18Integrated circuit having a Fin structure
#4 | 2008-11-20Integrated circuits; methods for manufacturing an integrated circuit; memory modules; computing systems
#5 | 2008-10-23Integrated circuits and methods of manufacturing thereof
#6 | 2008-10-16Integrated circuits and methods of manufacture
#7 | 2008-03-27Memory array having an interconnect and method of manufacture
#8 | 2008-03-27Memory cell arrangements
#9 | 2008-03-06Integrated circuit including a gate electrode
#10 | 2007-07-12Production method for a FinFET transistor arrangement, and corresponding FinFET transistor arrangement
#11 | 2007-02-01Semiconductor memory with charge-trapping stack arrangement
#12 | 2007-01-25Non-volatile memory cells and methods for fabricating non-volatile memory cells
#13 | 2006-11-30Semiconductor memory component with body region of memory cell having a depression and a graded dopant concentration
#14 | 2006-05-25NROM semiconductor memory device and fabrication method
#15 | 2006-01-05Fin field effect transistor memory cell
#16 | 2005-12-15Memory cell, memory cell arrangement, patterning arrangement, and method for fabricating a memory cell
#17 | 2005-10-13Integrated circuit array
#18 | 2005-08-25High-density NROM-FINFET
#19 | 2005-07-21Method for the production of a memory cell, memory cell and memory cell arrangement
#20 | 2005-07-07Flash memory cell and fabrication method
#21 | 2005-06-30Non-volatile flash semiconductor memory and fabrication method
#22 | 2005-05-26Method for producing a substrate
#23 | 2005-03-03Floating gate memory cell with a metallic source/drain and gate, and method for manufacturing such a floating gate memory gate cell
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