Craig E. Hampel

CONFIGURABLE IN-ARRAY EVENT TRACKING

FLEXIBLE METADATA ALLOCATION AND CACHING

MEMORY MODULE WITH REDUCED READ/WRITE TURNAROUND OVERHEAD

MULTIPLE PRECISION MEMORY SYSTEM

CONFIGURABLE IN-ARRAY EVENT TRACKING

Memory error detection

MEMORY SYSTEM WITH ACTIVATE-LEVELING METHOD

High-performance, high-capacity memory systems and modules

Dynamically configurable memory error control schemes

Compressed memory buffer device

Periodic Calibration For Communication Channels By Drift Tracking

Memory controller for micro-threaded memory operations

SECURING DYNAMIC RANDOM ACCESS MEMORY (DRAM) CONTENTS TO NON-VOLATILE IN A PERSISTENT MEMORY MODULE

Memory error detection

COMMUNICATION CHANNEL CALIBRATION FOR DRIFT CONDITIONS

Memory module with reduced read/write turnaround overhead

Periodic calibration for communication channels by drift tracking

Memory system with activate-leveling method

Multiple precision memory system

Memory error detection

Signaling system with adaptive timing calibration

Communication channel calibration for drift conditions

High-performance, high-capacity memory systems and modules

Memory module with reduced read/write turnaround overhead

Performing cryptographic data processing operations in a manner resistant to external monitoring attacks

Memory component with pattern register circuitry to provide data patterns for calibration

Periodic calibration for communication channels by drift tracking

Securing address information in a memory controller

Memory controller for selective rank or subrank access

Signaling system with adaptive timing calibration

MEMORY CONTROLLER

Enhancements to improve side channel resistance

Communication channel calibration for drift conditions

Memory module with reduced read/write turnaround overhead

Periodic calibration for communication channels by drift tracking

Enhancements to improve side channel resistance

IMPLEMENTING ACCESS CONTROL BY SYSTEM-ON-CHIP

Signaling system with adaptive timing calibration

Memory error detection

Performing cryptographic data processing operations in a manner resistant to external monitoring attacks

Periodic calibration for communication channels by drift tracking

Memory controller for micro-threaded memory operations

Memory controller

Communication channel calibration for drift conditions

Memory module with reduced read/write turnaround overhead

Memory component with pattern register circuitry to provide data patterns for calibration

Memory controller for selective rank or subrank access

Memory system with activate-leveling method

Flash controller to provide a value that represents a parameter to a flash memory

Memory error detection

FLASH CONTROLLER TO PROVIDE A VALUE THAT REPRESENTS A PARAMETER TO A FLASH MEMORY

Memory controller

Memory component with pattern register circuitry to provide data patterns for calibration

High Performance, High Capacity Memory Systems and Modules

Communication channel calibration for drift conditions

Memory controller for selective rank or subrank access

Periodic calibration for communication channels by drift tracking

Memory controller for micro-threaded memory operations

Memory Controller For Selective Rank Or Subrank Access

Memory module with reduced read/write turnaround overhead

Performing cryptographic data processing operations in a manner resistant to external monitoring attacks

Signaling system with adaptive timing calibration

Memory controller

Flash controller to provide a value that represents a parameter to a flash memory

Implementing access control by system-on-chip

Memory component with pattern register circuitry to provide data patterns for calibration

Memory controller

Communication channel calibration for drift conditions

Implementing access control by system-on-chip

Flash controller to provide a value that represents a parameter to a flash memory

Memory error detection

Memory component with pattern register circuitry to provide data patterns for calibration

Integrated circuit authentication

Periodic calibration for communication channels by drift tracking

Memory systems with multiple modules supporting simultaneous access responsive to common memory commands

Memory system with activate-leveling method

Communication channel calibration for drift conditions

Chip storing a value that represents adjustment to output drive strength

Chip having register to store value that represents adjustment to output drive strength

Chip having port to receive value that represents adjustment to output driver parameter

Chip having port to receive value that represents adjustment to transmission parameter

Memory controller for selective rank or subrank access

Periodic calibration for communication channels by drift tracking

Memory module

Reconfigurable memory system data strobes

Method and system for synchronizing address and control signals in threaded memory modules

Chip having register to store value that represents adjustment to reference voltage

Memory controller for micro-threaded memory operations

Low power memory device

Printed-circuit board supporting memory systems with multiple data-bus configurations

Communication channel calibration for drift conditions

Memory error detection

Periodic calibration for communication channels by drift tracking

Memory error detection

Memory controller that enforces strobe-to-strobe timing offset

Independent Threading Of Memory Devices Disposed On Memory Modules

Memory component with pattern register circuitry to provide data patterns for calibration

Memory component that samples command/address signals in response to both edges of a clock signal

Memory modules and devices supporting configurable data widths

Memory component with terminated and unterminated signaling inputs