Ely K. Tsern

MEMORY COMPONENT WITH ADJUSTABLE CORE-TO-INTERFACE DATA RATE RATIO

MEMORY CONTROLLER WITH ERROR DETECTION AND RETRY MODES OF OPERATION

MEMORIES AND MEMORY COMPONENTS WITH INTERCONNECTED AND REDUNDANT DATA INTERFACES

MEMORY CONTROLLER SUPPORTING NONVOLATILE PHYSICAL MEMORY

Memory controller with error detection and retry modes of operation

Memories and memory components with interconnected and redundant data interfaces

Memory component with adjustable core-to-interface data rate ratio

Process for Making a Semiconductor System

Memory component with pattern register circuitry to provide data patterns for calibration

Memory controller supporting nonvolatile physical memory

MEMORY CONTROLLER

MEMORY CONTROL COMPONENT WITH INTER-RANK SKEW TOLERANCE

Memory controller with error detection and retry modes of operation

Memories and memory components with interconnected and redundant data interfaces

Memory controller

Memory controller supporting nonvolatile physical memory

Memory component with pattern register circuitry to provide data patterns for calibration

Memory component with multiple command/address sampling modes

Memory controller with error detection and retry modes of operation

Memory component with adjustable core-to-interface data rate ratio

Memory control component with dynamic command/address signaling rate

Semiconductor system

Memories and memory components with interconnected and redundant data interfaces

Memory controller

Memory component with pattern register circuitry to provide data patterns for calibration

Memory control component with inter-rank skew tolerance

Memory controller

Memory component with pattern register circuitry to provide data patterns for calibration

Memory controller supporting nonvolatile physical memory

Memory controller

Memory controller with error detection and retry modes of operation

Memory chip with error detection and retry modes of operation

Memory system with error detection and retry modes of operation

Controller device for use with electrically erasable programmable memory chip with error detection and retry modes of operation

Memory component with pattern register circuitry to provide data patterns for calibration

Memory systems with multiple modules supporting simultaneous access responsive to common memory commands

Stacked die package with aligned active and passive through-silicon vias

Memory component with adjustable core-to-interface data rate ratio

High capacity memory systems with inter-rank skew tolerance

Memory module

Low power memory device

Method of making a stacked device assembly

Printed-circuit board supporting memory systems with multiple data-bus configurations

Memory controller supporting nonvolatile physical memory

Memory controller that enforces strobe-to-strobe timing offset

Memory component with pattern register circuitry to provide data patterns for calibration

Memory component with pattern register circuitry to provide data patterns for calibration

Memory component that samples command/address signals in response to both edges of a clock signal

Memory modules and devices supporting configurable data widths

Memory component with terminated and unterminated signaling inputs

Memory module

Memory system with error detection and retry modes of operation

Memory controller with selective data transmission delay

Low Power Memory Device

Controlling DRAM at time DRAM ready to receive command when exiting power down

Memory controller

Memory apparatus supporting multiple width configurations

Memory device having multiple power modes

Memory Device Having Multiple Power Modes

Asynchronous pipelined memory access

Phase adjustment apparatus and method for a memory device signaling system

Process for making a semiconductor system

Memory system with error detection and retry modes of operation

Method of controlling a memory device having multiple power modes

Control component for controlling a delay interval within a memory component

Variable-width memory

Low power memory device

Memory Systems and methods supporting volatile and wear-leveled nonvolatile physical memory

Upgradable system with reconfigurable interconnect

Memory device having multiple power modes

Phase adjustment apparatus and method for a memory device signaling system

Memory controller with refresh logic to accommodate low-retention storage rows in a memory device

Upgradable memory system with reconfigurable interconnect

Asynchronous, high-bandwidth memory component using calibrated timing elements

Gesture-based power management of a wearable portable electronic device with display

Situationally aware and self-configuring electronic data and communication device

Phase adjustment apparatus and method for a memory device signaling system

Method and apparatus for signaling between devices of a memory system

Process for making a semiconductor system having devices that have contacts on top and bottom surfaces of each device

Memory module with termination component

Method and apparatus for signaling between devices of a memory system

Method and apparatus for adjusting the performance of a synchronous memory system

Asynchronous, high-bandwidth memory component using calibrated timing elements

Low power memory device

Partitioned game console system

Power control system for synchronous memory device

Memory Device Having a Delay Locked Loop and Multiple Power Modes

Memory controller device having timing offset capability

Clocked memory system with termination component

Point-to-point connection topology for stacked devices

Expandable slave device system with buffered subsystems

Memory Device Having a Configurable Oscillator for Refresh Operation

Apparatus and method for pipelined memory operations

Method and apparatus for coordinating memory operations among diversely-located memory components

Expandable slave device system

Method and apparatus for adjusting the performance of a synchronous memory system

Memory with refresh cycle donation to accommodate low-retention-storage rows

Memory with address-differentiated refresh rate to accommodate low-retention storage rows

Memory device testing to support address-differentiated refresh rates

Low power memory device