Inventor profile of:

Yan Wang

City:

San Jose, California

Country:

United States

Published Applications:

24

Last publication date:

2025-07-31

Top Assignees for applications by Yan Wang

The entities that hold a legal rights for patent applications filed by inventor Wang Yan:

Recent patent applications by Wang Yan

Yan Wang from San Jose, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2025-07-31
US20250245279A1
Physics

AUGMENTED FOLLOW PROBABILITY FOR SOCIAL NETWORKING SYSTEM FOLLOW RECOMMENDATIONS

#2 | 2024-11-07
US20240369356A1
Physics

INSPECTION APPARATUS AND METHOD

#3 | 2024-09-26
US20240321827A1
Electricity

THERMALLY AWARE STACKING TOPOLOGY

#4 | 2024-09-26
US20240321702A1
Electricity

BACKSIDE POWER

#5 | 2024-09-26
US20240321668A1
Electricity

TEMPERATURE SENSORS IN DIE PAIR TOPOLOGY

#6 | 2024-07-30
US17990353
Electricity

Controlling interface of a multi-input modality device

#7 | 2023-10-05
US20230317529A1
Electricity

METHOD OF TESTING STRUCTURES AND STACKING WAFERS

#8 | 2023-05-16
US16941422
Physics

Wafer testing and structures for wafer testing

#9 | 2023-03-30
US20230096657A1
Electricity

LEVELING SENSOR IN MULTIPLE CHARGED-PARTICLE BEAM INSPECTION

#10 | 2022-12-06
US17106560
Electricity

Controlling interface of a multi-input modality device

#11 | 2022-11-22
US16717708
Electricity

Embedded shield for protection of memory cells

#12 | 2022-04-07
US20220107176A1
Physics

Inspection apparatus and method

#13 | 2018-04-12
US20180102354A1
Electricity

Method, apparatus, and system for two-dimensional power rail to enable scaling of a standard cell

#14 | 2017-06-13
US15077564
Electricity

Method of forming self aligned continuity blocks for mandrel and non-mandrel interconnect lines

#15 | 2016-11-17
US20160335389A1
Physics

Method, apparatus, and system for improved standard cell design and routing for improving standard cell routability

#16 | 2016-10-18
US15060691
Electricity

Methods to utilize merged spacers for use in fin generation in tapered IC devices

#17 | 2014-05-15
US20140131816A1
Electricity

Cross-coupling-based design using diffusion contact structures

#18 | 2013-11-07
US20130292773A1
Electricity

Cross-coupling-based design using diffusion contact structures

#19 | 2013-10-17
US20130275935A1
Physics

Providing timing-closed FinFET designs from planar designs

#20 | 2012-12-06
US20120306530A1
Physics

Electronic device board level security

#21 | 2012-09-13
US20120229480A1
Physics

Regulation of screen composing in a device

#22 | 2012-09-11
US12141543
-

System and method for detecting mask data handling errors

#23 | 2009-08-27
US20090212813A1
Physics

Electronic device board level security

#24 | 2009-01-22
US20090022079A1
Electricity

Method and apparatus for providing enhanced channel interleaving

InventorID:

490827 ⎘