Los Altos, California
United States
30
2015-02-12
The entities that hold a legal rights for patent applications filed by inventor Johnson Mark G.:
Mark G. Johnson from Los Altos, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Dense arrays and charge storage devices
#2 | 2014-08-28Three-dimensional nonvolatile memory and method of fabrication
#3 | 2014-08-14Dense arrays and charge storage devices
#4 | 2014-08-07Dense arrays and charge storage devices
#5 | 2013-11-28Pillar-shaped nonvolatile memory and method of fabrication
#6 | 2013-11-05Silicon nitride antifuse for use in diode-antifuse memory arrays
#7 | 2012-10-04Vertically stacked field programmable nonvolatile memory and method of fabrication
#8 | 2012-09-06Dense arrays and charge storage devices
#9 | 2011-06-30DENSE ARRAYS AND CHARGE STORAGE DEVICES
#10 | 2011-01-27Vertically stacked field programmable nonvolatile memory and method of fabrication
#11 | 2010-07-08Integrated circuit incorporating decoders disposed beneath memory arrays
#12 | 2009-07-09Three terminal nonvolatile memory device with vertical gated diode
#13 | 2008-06-03System architecture and method for three-dimensional memory
#14 | 2007-09-27Methods for adaptive trip point detection
#15 | 2007-09-20Apparatus for adaptive trip point detection
#16 | 2007-04-10Three-dimensional memory device with ECC circuitry
#17 | 2006-10-31Dense arrays and charge storage devices
#18 | 2006-10-19Apparatus and methods for adaptive trip point detection
#19 | 2006-08-24Delay locked loop circuitry for clock delay adjustment
#20 | 2006-05-02Delay locked loop circuitry for clock delay adjustment
#21 | 2005-10-11Integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions
#22 | 2005-05-31Method for altering a word stored in a write-once memory device
#23 | 2005-05-19Integrated circuit incorporating three-dimensional memory array with dual opposing decoder arrangement
#24 | 2005-05-03Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication
#25 | 2005-04-19Monolithic three dimensional array of charge storage devices containing a planarized surface
#26 | 2005-04-14Multiple twin cell non-volatile memory array and logic block structure and method therefor
#27 | 2005-03-24Memory device and method for simultaneously programming and/or reading memory cells on different levels
#28 | 2005-03-15Redundant memory structure using bad bit pointers
#29 | 2005-03-15Modular memory device
#30 | 2005-02-24Redundant memory structure using bad bit pointers
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