Inventor profile of:

Mark G. Johnson

City:

Los Altos, California

Country:

United States

Published Applications:

30

Last publication date:

2015-02-12

Top Assignees for applications by Mark G. Johnson

The entities that hold a legal rights for patent applications filed by inventor Johnson Mark G.:

Recent patent applications by Johnson Mark G.

Mark G. Johnson from Los Altos, US has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2015-02-12
US20150044833A1
Electricity

Dense arrays and charge storage devices

#2 | 2014-08-28
US20140239248A1
Electricity

Three-dimensional nonvolatile memory and method of fabrication

#3 | 2014-08-14
US20140225180A1
Electricity

Dense arrays and charge storage devices

#4 | 2014-08-07
US20140217491A1
Electricity

Dense arrays and charge storage devices

#5 | 2013-11-28
US20130314970A1
Physics

Pillar-shaped nonvolatile memory and method of fabrication

#6 | 2013-11-05
US10610804
-

Silicon nitride antifuse for use in diode-antifuse memory arrays

#7 | 2012-10-04
US20120250396A1
Physics

Vertically stacked field programmable nonvolatile memory and method of fabrication

#8 | 2012-09-06
US20120223380A1
Electricity

Dense arrays and charge storage devices

#9 | 2011-06-30
US20110156044A1
Electricity

DENSE ARRAYS AND CHARGE STORAGE DEVICES

#10 | 2011-01-27
US20110019467A1
Physics

Vertically stacked field programmable nonvolatile memory and method of fabrication

#11 | 2010-07-08
US20100171152A1
Physics

Integrated circuit incorporating decoders disposed beneath memory arrays

#12 | 2009-07-09
US20090173985A1
Electricity

Three terminal nonvolatile memory device with vertical gated diode

#13 | 2008-06-03
US10774758
-

System architecture and method for three-dimensional memory

#14 | 2007-09-27
US20070222482A1
Electricity

Methods for adaptive trip point detection

#15 | 2007-09-20
US20070216448A1
Electricity

Apparatus for adaptive trip point detection

#16 | 2007-04-10
US10840815
-

Three-dimensional memory device with ECC circuitry

#17 | 2006-10-31
US10842008
-

Dense arrays and charge storage devices

#18 | 2006-10-19
US20060232304A1
Electricity

Apparatus and methods for adaptive trip point detection

#19 | 2006-08-24
US20060188051A1
Electricity

Delay locked loop circuitry for clock delay adjustment

#20 | 2006-05-02
US10366865
-

Delay locked loop circuitry for clock delay adjustment

#21 | 2005-10-11
US10307270
-

Integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions

#22 | 2005-05-31
US10023200
-

Method for altering a word stored in a write-once memory device

#23 | 2005-05-19
US20050105371A1
Physics

Integrated circuit incorporating three-dimensional memory array with dual opposing decoder arrangement

#24 | 2005-05-03
US9927642
-

Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication

#25 | 2005-04-19
US9927648
-

Monolithic three dimensional array of charge storage devices containing a planarized surface

#26 | 2005-04-14
US20050078514A1
Physics

Multiple twin cell non-volatile memory array and logic block structure and method therefor

#27 | 2005-03-24
US20050063220A1
Physics

Memory device and method for simultaneously programming and/or reading memory cells on different levels

#28 | 2005-03-15
US10402385
-

Redundant memory structure using bad bit pointers

#29 | 2005-03-15
US10342122
-

Modular memory device

#30 | 2005-02-24
US20050044459A1
Physics

Redundant memory structure using bad bit pointers

InventorID:

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