Jared L. Zerbe

COMPENSATING FOR ON-CHIP POWER SUPPLY VOLTAGE TRANSIENTS

Multi-Die Fine Grain Integrated Voltage Regulation

Split-path equalizer and related methods, devices and systems

LOW-POWER SOURCE-SYNCHRONOUS SIGNALING

Clock Generation for Timing Communications with Ranks of Memory Devices

USING DYNAMIC BURSTS TO SUPPORT FREQUENCY-AGILE MEMORY INTERFACES

Multi-Die Fine Grain Integrated Voltage Regulation

Low power edge and data sampling

Low-power source-synchronous signaling

Systems, methods and apparatus for through skin communication and noise disambiguation

Clock generation for timing communications with ranks of memory devices

PARTIAL RESPONSE RECEIVER

Using dynamic bursts to support frequency-agile memory interfaces

Split-path equalizer and related methods, devices and systems

Low power edge and data sampling

Detecting power supply noise events and initiating corrective action

Low-power source-synchronous signaling

HIGH-SPEED SIGNALING SYSTEMS WITH ADAPTABLE PRE-EMPHASIS AND EQUALIZATION

Methods and circuits for asymmetric distribution of channel equalization between devices

Multi-die fine grain integrated voltage regulation

Partial response receiver

Selectable-tap equalizer

Using dynamic bursts to support frequency-agile memory interfaces

Clock generation for timing communications with ranks of memory devices

Low power edge and data sampling

Methods and circuits for asymmetric distribution of channel equalization between devices

Split-path equalizer and related methods, devices and systems

Multi-mode clock multiplier

Selectable-tap equalizer

Downshift techniques for oscillator with feedback loop

Detecting power supply noise events and initiating corrective action

Method and apparatus for source-synchronous signaling

Receiver with clock recovery circuit and adaptive sample and equalizer timing

Integrated circuit comprising circuitry to change a clock signal frequency while a data signal is valid

Low-power source-synchronous signaling

Using a stuttered clock signal to reduce self-induced voltage noise

Multi-die fine grain integrated voltage regulation

Selectable-tap equalizer

Downshift techniques for oscillator with feedback loop

Partial response receiver

Integrated circuit comprising circuitry to change a clock signal frequency while a data signal is valid

Frequency-agile clock generator

Method and apparatus for source-synchronous signaling

Frequency-agile clock multiplier

High-speed signaling systems with adaptable pre-emphasis and equalization

Clock generation for timing communications with ranks of memory devices

Methods and circuits for asymmetric distribution of channel equalization between devices

Flash controller to provide a value that represents a parameter to a flash memory

Receiver with time-varying threshold voltage

Selectabe-tap equalizer

Using dynamic bursts to support frequency-agile memory interfaces

High-speed signaling systems with adaptable pre-emphasis and equalization

Multi-die fine grain integrated voltage regulation

Partial response receiver

Low power edge and data sampling

Phase control block for managing multiple clock domains in systems with frequency offsets

Methods and circuits for asymmetric distribution of channel equalization between devices

Integrated circuit comprising circuitry to change a clock signal frequency while a data signal is valid

Receiver with time-varying threshold voltage

FLASH CONTROLLER TO PROVIDE A VALUE THAT REPRESENTS A PARAMETER TO A FLASH MEMORY

Clock generator with injection-locking oscillators

Selectable-tap equalizer

Detecting power supply noise events and initiating corrective action

Method and apparatus for source-synchronous signaling

Run-time output clock determination

Using proxies to enable on-device machine learning

Integrated circuit comprising circuitry to determine settings for an injection-locked oscillator

High-speed signaling systems with adaptable pre-emphasis and equalization

Receiver with clock recovery circuit and adaptive sample and equalizer timing

Selectable-tap equalizer

Downshift techniques for oscillator with feedback loop

Multi-PAM output driver with distortion compensation

Phase control block for managing multiple clock domains in systems with frequency offsets

Integrated circuit having a multiplying injection-locked oscillator

Using dynamic bursts to support frequency-agile memory interfaces

Clock generation for timing communications with ranks of memory devices

Low-power source-synchronous signaling

Multi-die fine grain integrated voltage regulation

Selectable-tap equalizer

Methods and circuits for asymmetric distribution of channel equalization between devices

Receiver with Clock Recovery Circuit and Adaptive Sample and Equalizer Timing

Flash controller to provide a value that represents a parameter to a flash memory

Frequency-agile clock multiplier

Partial response receiver

Jitter-based clock selection

Split-path equalizer and related methods, devices and systems

Integrated circuit comprising circuitry to change a clock signal frequency while a data signal is valid

Receiver with clock recovery circuit and adaptive sample and equalizer timing

Clock generation for timing communications with ranks of memory devices

Integrated circuit having a multiplying injection-locked oscillator

Phase control block for managing multiple clock domains in systems with frequency offsets

Selectable-tap equalizer

Flash controller to provide a value that represents a parameter to a flash memory

Clock recovery circuit

Methods and circuits for asymmetric distribution of channel equalization between devices

Integrated circuit comprising circuitry to determine settings for an injection-locked oscillator

Integrated circuit comprising frequency change detection circuitry

Partial response receiver

Fast-wake memory control

Chip storing a value that represents adjustment to output drive strength