San Jose, California
United States
17
2014-04-17
The entities that hold a legal rights for patent applications filed by inventor Pavisic Ivan:
Ivan Pavisic from San Jose, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smaller
#2 | 2012-11-01Method and computer program for generating grounded shielding wires for signal wiring
#3 | 2011-10-20Method and apparatus for balancing signal delay skew
#4 | 2009-10-01Methods and apparatus for fast unbalanced pipeline architecture
#5 | 2009-07-23Signal delay skew reduction system
#6 | 2008-05-08Built in self test transport controller architecture
#7 | 2008-01-17Density driven layout for RRAM configuration module
#8 | 2007-07-05System for avoiding false path pessimism in estimating net delay for an integrated circuit design
#9 | 2006-08-24Method of buffer insertion to achieve pin specific delays
#10 | 2006-08-24Optimizing IC clock structures by minimizing clock uncertainty
#11 | 2006-08-15Method and system for classifying an integrated circuit for optical proximity correction
#12 | 2006-06-08Density driven layout for RRAM configuration module
#13 | 2006-05-18Memory tiling architecture
#14 | 2006-04-20Compact custom layout for RRAM column controller
#15 | 2006-04-11RRAM backend flow
#16 | 2005-09-06Clock tree synthesis with skew for memory devices
#17 | 2005-01-13Optimizing IC clock structures by minimizing clock uncertainty
725010 ⎘